A.H. Montree

Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors

This paper presents new insights into the mechanisms of gate depletion and boron penetration in deep submicron CMOS technologies. MOSFET matching measurements show that these effects are stochastic in nature, and are associated with the gate poly-Si grain size distribution. Moreover, this work demonstrates that these effects can strongly degrade transistor matching performance of future CMOS generations.

A 25 mu m/sup 2/ bulk full CMOS SRAM cell technology with fully overlapping contacts

The authors describe a 25.2 mu m/sup 2/ bulk full CMOS SRAM cell for application in high-density static memories fabricated in a 14-mask process using minimum dimensions of 0.5 mu m at a comparatively relaxed 1.2 mu m pitch. A very aggressive n/sup +//p/sup +/ spacing and a fully overlapping contact technology are the key elements used to achieve a competitive cell area. The functionality of the cell was shown on a 1 kb test memory.<<ETX>>

N/sub 2/O nitrided gate dielectric technology for 0.25 mu m CMOS

A technology for thin N/sub 2/O nitrided gate oxide was developed for 0.25 mu m CMOS. A gate dielectric of 7.5 nm thickness was grown using a two-step furnace process. The first step is oxidation in diluted dry oxygen at 900 degrees C, the second step is nitridation in pure N/sub 2/O at 950 degrees C. The use of lightly nitrided gate dielectrics improved the gate oxide quality and did not degrade the MOS device properties. Furthermore, boron diffusion through the thin dielectric of BF/sub 2/ doped poly gates was suppressed by N/sub 2/O nitridation.<<ETX>>

Lightly nitrided gate oxides for 0.25 mm CMOS

Abstract A N 2 O lightly nitrided gate dielectric technology is developed for 0.25 μm CMOS. Gate dielectric with a thickness of 7.5 nm is grown in a two-step furnace process. The first step is oxidation in diluted dry oxygen at 900° C , the second step is nitridation in pure N 2 O at 950° C . The use of lightly nitrided gate dielectrics improves the gate oxide quality and has no adverse effects on devices. Furthermore boron diffusion through thin gate oxide of BF + 2 doped poly gates is suppressed. This makes it possible to use low energy BF + 2 implants for shallow drain formation. The physical and electrical characterisation of MOS capacitors and 0.25 μm transistors will be presented.

Dopant profile engineering of advanced Si MOSFET’s using ion implantation

Abstract Ion implantation has been used to realize non-uniform, steep retrograde (SR) dopant profiles in the active channel region of advanced Si MOSFET’s. After defining the transistor configuration, SR profiles were formed by dopant implantation through the polycrystalline Si gate and the gate oxide (through-the-gate, TG, implantation). The steep nature of the as-implanted profile was retained by applying rapid thermal annealing for dopant activation and implantation damage removal. For NMOS transistors, TG implantation of B yields improved transistor performance through increased carrier mobility, reduced junction capacitances, and reduced susceptibility to short-channel effects. Electrical measurements show that the gate oxide quality is not deteriorated by the ion-induced damage, demonstrating that transistor reliability is preserved. For PMOS transistors, TG implantation of P or As leads to unacceptable source/drain junction broadening as a result of transient enhanced dopant diffusion during thermal activation.

Oxidation enhanced diffusion during the growth of ultrathin oxides

Abstract Boron-doped marker layers grown by chemical vapor deposition were used to measure oxidation enhanced diffusion (OED) during the growth of ultrathin oxide layers of 3.3 nm. The oxides were grown by three different methods: steam oxidation at 650°C, dry furnace oxidation at 800°C and rapid thermal oxidation at 1050°C. The effective B diffusion length decreases drastically with oxidation temperature, being lower than ∼3 nm for steam oxidation. This demonstrates that steam oxidation is ideally suited for minimizing dopant diffusion during the growth of gate oxides in advanced CMOS processing. Diffusion analysis shows that the enhancement in the equilibrium diffusivity increases from a factor of ∼3 at 1050°C to ∼350 at 650°C. On the basis of these measurements, parameters in a state-of-the-art OED model have been calibrated to enable accurate process modeling of OED in the regime of thin oxide growth.

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 /spl mu/m CMOS low-voltage applications

We have studied an aggressive lateral MOS channel profiling combined with gate work function engineering for sub-0.13 /spl mu/m generation PMOSFETs oriented for low-voltage operation. In this scheme, the Ge fraction in the poly-SiGe gate was used to control threshold voltage V/sub T/, while short channel effects (SCE) were completely suppressed down to 100 nm gate lengths by heavily doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no V/sub T/ roll-off behaviour, and 67 mV/dec sub-V/sub T/ voltage swing. The low channel doping leads to significant improvements in the channel mobility and parasitic capacitances, resulting in excellent I/sub on//I/sub off/ behaviour and record ring oscillator delays for low-voltage operation. Process variation analysis confirmed the high manufacturing potential for the approach suggested. The approach can be extended to n-type devices with a suitable choice of gate work function.

Comparison of buried and surface channel PMOS devices for low voltage 0.5 mu m CMOS

A low voltage option in a 0.5 mu m CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n/sup +/-gate buried channel devices are compared with the corresponding p/sup +/-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n/sup +/-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 mu m physical gate length PMOS transistor with less then 0.1 nA/ mu m leakage current was realised in a 0.5 mu m CMOS process.<<ETX>>

Making 50 nm transistors with 248 nm lithography

Using a novel phase-shift mask, 50 nm resolution has been achieved with conventional 248 nm lithography. The addition of so-called scattering bars enables within-die control of linewidths from 250 to 50 nm. Using 200 nm thick resist layers combined with hard mask processing, transistors with gate-lengths down to 50 nm have been fabricated. Well controlled device performance is achieved by optimizing offset spacers and pocket implants.

Channel formation for 0.15 /spl mu/m CMOS using through-the-gate implantation

Front-end optimization of a 0.15 /spl mu/m CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 /spl mu/m CMOS transistor and circuit performance was obtained.