Hanyi Ding

Through-silicon vias enable next-generation SiGe power amplifiers forwireless communications

We feature a 0.35-µm SiGe BiCMOS technology (SiGe 5PAe) that is optimized for power amplifier (PA) applications. The key feature of this technology is a novel low-inductance ground to the package using through-silicon vias (TSVs) that results in a competitive solution for future multiband and multimode PA integration. The tungsten-filled, multifinger, bar-shaped TSV delivers more than a 75% reduction in inductance compared to a traditional wirebond. This enables higher frequency applications with a roughly 20% reduction in die area without compromising the technology reliability for use conditions in a low-cost plastic QFN (quad flat no leads) package. In this paper we demonstrate the commercial feasibility of the TSV, its RF performance, its reliability, and its usefulness in a demanding WiMAX® (Worldwide Interoperability for Microwave Access) PA application.

A BiCMOS Technology Featuring a 300/330 GHz (fT/fmax) SiGe HBT for Millimeter Wave Applications

The paper presents a 0.13 mum SiGe BiCMOS technology for millimeter wave applications. This technology features a high performance HBT (fT = 300 GHz /fmax = 330 GHz) along with various newly developed millimeter wave features, such varactor, Schottky and p-i-n diodes and other back end of line passives

CMOS millimeter wave phase shifter based on tunable transmission lines

This paper presents a tunable transmission line (t-line) structure, featuring independent control of line inductance and capacitance. The t-line provides variable delay while maintaining relatively constant characteristic impedance using direct digital control through FET switches. As an application of this original structure, a 60 GHz RF-phase shifter for phased-array applications is implemented in a 32 nm SOI process attaining state-of-the-art performance. Measured data from two phase shifter variants at 60 GHz showed phase changes of 175° and 185°, S21 losses of 3.5-7.1 dB and 6.1-7.6 dB, RMS phase errors of 2° and 3.2°, and areas of 0.073 mm2 and 0.099 mm2 respectively.

Novel low-cost on-chip CPW slow-wave structure for compact RF components and mm-wave applications

In this paper, an ideal slow wave coplanar waveguide (CPW) structures with low losses, moderate impedance and CMOS fabrication technology have been developed. The slow wave CPW transmission line structures were achieved through IBM 0.13 mum technology with multi-layer metals. The CPW were implemented with narrower signal line or wider separation between signal and ground plane to increase the inductance per unit length, while metal strips on another metal layers cross under/above the CPW lines, which are orthogonal to signal propagation direction. Losses reduction using via bars to increase the thickness of the signal metal layer, structures with metal strip options (above, under and both CPW) to increase the capacitance per unit length of the CPW and provide more flexibility for the proposed structure, effect of the metal strips pitch are also discussed. The slow wave structure discussed in this paper can shrink the side dimension of the mm-wave passive components by up to 35%.

Modeling and implementation of on-chip millimeter-wave compact branch line couplers in a BiCMOS technology

In this paper, the modeling, design, and measurement of on-chip compact millimeter-wave branch line couplers are discussed. These couplers are realized with the Back End of Line (BEOL) wiring and enabled as a library device of a 0.13 micron SiGe BiCMOS process design kit. Like other library devices, this coupler device has a scalable layout pattern and a schematic symbol, which allows users to have couplers at different frequencies by inputting the dimensions. An accurate model for these branch line couplers is developed, which shows a good match with the measurements of the couplers designed for 60 GHz, 77 GHz and 94 GHz. Better than 19 dB return loss, better than 1.5 dB insertion loss and better than 21dB isolation have been observed. The side dimensions of these compact on-chip couplers are ranging from 440 microns to 530 microns.

On-Chip Millimeter-Wave Library Device - Scalable Wilkinson Power Divier/Combiner

On-chip millimeter wave Wilkinson power divider has been developed with the back end of line (BEOL) wiring and enabled as a library device in a 0.13 mum BiCMOS process design kit. The device layout and model are fully scalable, i.e. users can design a power divider at different frequencies or in different reference characteristic impedance systems by inputting the dimensions. Excellent model and hardware correlation has been observed up to 110 GHz. The measured results show that very good performance on-chip Wilkinson power dividers have been obtained in this technology, such as less than about 0.1 dB amplitude imbalance, about 0.8 dB of insertion loss with bandwidth of about 15% of the design frequency (defined at 15 dB return loss level) and about 20 dB of isolations. In addition, the device is the design rule check (DRC) clean and the layout versus schematic (LVS) enabled, which help to shorten the design cycle.

Wideband on-chip RF MEMS switches in a BiCMOS technology for 60 GHz applications

In this paper, an on-chip RF MEMS capacitive switch is designed and simulated with a 0.13 mum IBM SiGe BiCMOS technology for the first time. Mechanical and electrical design of the high frequency switch are discussed in this paper. Special consideration to improve Con/Coff ratio of the switch is used with multi metal layers configuration. The switch is designed for 60 GHz wireless applications, the results show that the switch has the insertion loss is less than 0.2 dB when the switch is off, while the isolation loss is larger than 15 dB when the switch is on over the frequency from 40 to 70 GHz. The calculated pull-in voltage of the switch is only about 10 volts, the switch is compact comparing with the reported PIN diode RF switch and has the membrane dimension of 10 mum x 240 mum.

Novel on-chip high performance slow wave structure using discontinuous microstrip lines and multi-layer ground for compact millimeter wave applications

In this paper, a novel on chip slow wave structure is developed. It is built with discontinuous microstrip steps, the discontinuous line is made by placing a wide and short line and a narrow and short line in turn and the step discontinuity provides with additional inductance and capacitance. The slow wave transmission line structures were achieved through IBM 45 nm technology with multi-layer metals. Simulated and measured results for slow wave transmission line are provided in the paper for design with different characteristics impedances. Results have shown that the inductance per unit length and capacitance per unit length of the line increased about 50% compared with the conventional transmission line structure. In addition, the length effect of the wide and narrow signal sections is thoroughly studied and results have shown that the smaller the pitch, the better the slow wave effect which agrees with [7] very well. A 75 GHz Branchline coupler built with the slow wave transmission lines has also been designed, and the coupler is 70% smaller than the conventional design.

A high-resistivity SiGe BiCMOS technology for WiFi RF front-end-IC solutions

We present for the first time a novel high resistivity bulk SiGe BiCMOS technology that has been optimized for a WiFi RF front-end-IC (FEIC) integration. A nominally 1000 Ohm-cm p-type silicon substrate is utilized to integrate several SiGe HBTs for power amplifiers (PAs), a SiGe HBT low-noise amplifier (LNA), and isolated nFET RF switch device. Process elements include trench isolation for low-loss passives and reduced parasitic coupling, and a lower-resistivity region for the FETs to minimize changes to the circuit library.

Novel on-chip variable delay transmission line with fixed characteristic impedance

On-chip electronically controllable delay elements are often used in RF designs such as phased array antenna systems. This paper presents a novel on-chip variable delay transmission line structure with fixed characteristic impedance. EM simulations show a delay change of 15.6 % is possible while the characteristic impedance of the novel transmission line varies a maximum of 3.7% from the 50 Ω target between two possible delay states.