Zhong-Xiang He

A 0.18 /spl mu/m BiCMOS technology featuring 120/100 GHz (f/sub T//f/sub max/) HBT and ASIC-compatible CMOS using copper interconnect

A BiCMOS technology is presented that integrates a high performance NPN (f/sub T/=120 GHz and f/sub max/=100 GHz), ASIC compatible 0.11 /spl mu/m L/sub eff/ CMOS, and a full suite of passive elements. Significant HBT performance enhancement compared to previously published results has been achieved through further collector and base profile optimization guided by process and device simulations. Base transit time reduction was achieved by simultaneously increasing the Ge ramp and by limiting the base diffusion with the addition of carbon doping to SiGe epitaxial base. This paper describes IBMs next generation SiGe BiCMOS production technology targeted at the communications market.

A Thin-Film SOI 180nm CMOS RF Switch Technology

This paper describes a 180nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies. Index Terms — RF switch, thin film SOI, wireless, CMOS

Line edge roughness and spacing effect on low-k TDDB characteristics

The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced.

A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications

We present the electrical characteristics of the first 90nm SiGe BiCMOS technology developed for production in IBMs large volume 200mm fabrication line. The technology features 300 GHz fT and 360 GHz fMAX high performance SiGe HBTs, 135 GHz fT and 2.5V BVCEO medium breakdown SiGe HBTs, 90nm Low Power RF CMOS, and a full suite of passive devices. A design kit supports custom and analog designs and a library of digital functions aids logic and memory design. The technology supports mm-wave and high-performance RF/Analog applications.

Planar MEMS RF capacitor integration

MEMS capacitor switches have been integrated with high voltage CMOS ICs. The MEMS were formed with the final three AlCu wiring levels in SiO2 using a planar sacrificial silicon cavity process. The MEMS cavities were hermetically sealed at less than atmospheric pressure at wafer level. After Pb-free solder bumping, the MEMS chips are packaged in organic laminate packages. The capacitor portion of the MEMS beam has a capacitance density of ∼0.12fF/µm2 and the pull-in, restoring, self-actuation, and break down voltages are on the order of 25V, 10V, >45V, and >150V respectively. MEMS cycling lifetime over 250 Mcycles with no fails has been demonstrated. This paper summarizes the critical integration, yield, and reliability issues associated with developing this rf MEMS technology.

A 0.35 μm SiGe BiCMOS technology for power amplifier applications

In this paper we introduce, a state-of-the-art SiGe BiCMOS power amplifier technology that features two NPNs with 40 GHz / 6.0 V & 27 GHz / 8.5 V (fT - BVceo) respectively, a novel low inductance metal ground through-silicon-via (TSV), integrated on a low-cost 0.35 μm lithography node with 3.3 V / 5.0 V dual-gate CMOS technology and high-quality passives on a 50 Ω.cm substrate.

Improvements in SOI technology for RF switches

Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.

High and low density complimentary MIM capacitors fabricated simultaneously in advanced RFCMOS and BiCMOS technologies

Two MIM capacitors with capacitance density of 11 and 0.48 fF/um2 were fabricated simultaneously using IBM-s 0.13 um SiGe 8 WL BiCMOS process. Results from DC parametric measurement indicate that these two capacitors compliment each other extremely well.

ESD Testing of Aluminum and Copper Vertical Parallel plate (VPP) Capacitor Structures

Vertical parallel plate (VPP) capacitor elements are being used in RF components for RF CMOS and RF BiCMOS technologies. ESD robustness evaluation of the VPP capacitor is very important for RF applications when these elements are used on the input pads of RF receiver networks. In this paper, the first ESD measurements of VPP structures are shown for the first time. The purpose of the work is to evaluate the electrical response of the VPP structure for HBM, and transmission line pulse (TLP) waveforms. In addition, new discoveries are disclosed with aluminum and copper vertical parallel plate capacitor elements.

A 0.24 μm SiGe BiCMOS technology featuring 6.5V CMOS, f T /f MAX of 15/14 GHz VPNP, and f T /f MAX of 60/125 GHz HBT

For the first time, we report a 0.24 mum SiGe BiCMOS technology that offers full suite of active device including three distinct NPNs, a vertical PNP, CMOS supporting three different operating-voltages, and wide range of passive devices. In particular, this technology provides 6.5 V CMOS capability and VPNP with fT/fMAX of 15/14 GHz and BVCEO of 6.5 V which can be used to complement high breakdown NPN with fT of 30 GHz and BVceo of 6.0 V.