Jayashree Saxena

Minimizing power consumption in scan testing: pattern generation and DFT techniques

It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.

An analysis of power reduction techniques in scan testing

Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design.

Scan-based transition fault testing - implementation and low cost test challenges

The semiconductor industry as a whole is growing increasingly concerned about the possible presence of delay-inducing defects. There exist structured test generation and application techniques which can detect them, but there are many practical issues associated with their use. These problems are particularly acute when using low cost test equipment. In this paper, we describe an overall approach for implementing scan-based delay testing with emphasis on low-cost test.

A design for testability scheme to reduce test application time in full scan

Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time required by full scan could be high because of the necessity to scan in and scan out test vectors. In this paper, a hybrid scheme is presented that aims to reduce test application time in circuits with full scan. The proposed scheme exploits the inherent sequential nature of the circuit in conjunction with the additional controllability and observability available through full scan. Also, it is shown that the hybrid scheme has an additional advantage of being suited for testing transition faults.<<ETX>>

A method to derive compact test sets for path delay faults in combinational circuits

In path delay fault testing, the number of faults to be tested in a circuit is inherently very large. Therefore, deriving compact test sets for path delay faults is an important issue. This paper presents a method to derive compact test sets for path delay faults by using the notion of compatible faults. A technique to derive maximal compatible path delay fault sets is described. The technique is based on identifying necessary conditions on lines in a circuit along with values a line cannot take in order to test a given path. Experimental results on ISCAS benchmarks are presented to demonstrate the effectiveness of using this technique in reducing test set size.<<ETX>>

On applying non-classical defect models to automated diagnosis

Automated fault diagnosis based on the stuck-at fault model is not always effective. This paper presents practical experiences in applying a bridging fault based diagnosis technique to a TI ASIC design. Results are presented for units into which known bridging defects have been introduced via a focused ion beam (FIB) machine.

An empirical study on the effects of test type ordering on overall test efficiency

The order in which the various test types are applied can have an impact on the overall efficiency of the test operation. Furthermore, the speed at which the tests can be executed and the latency of defect detection are also important factors. In this paper, we evaluate an exhaustive set of test orderings over a variety of assumed execution parameters to analyze their effects on overall tester time consumption.

Bridging fault diagnosis in the absence of physical information

Effective bridging fault diagnosis requires reducing the (/sub 2//sup n/) number of bridging faults to a handful of candidates. A preliminary step can reduce the O(n/sup 2/) candidates to a manageable O(n) candidates by using layout information to eliminate those bridging faults that are very unlikely to be shorted together. This step removes from consideration those faults that match the fault signature but are physically impossible. However, sometimes-perhaps due to issues of intellectual property or because the degree of information stored about a circuit changes over its lifecycle-the physical design of the circuit is not available, and the number of nodes is too large to explicitly consider all pairs. In this paper we present two ways to provide successful diagnoses without access to physical information. The second method produces optimal diagnoses under our ranking criteria. Either technique can be used in conjunction with information extracted from the physical design to allow for diagnoses of much larger circuits than previously possible.

Automated diagnosis in testing and failure analysis

To meet market demands for the rapid introduction of new semiconductor products, automated means of diagnosing defective silicon are fast becoming mandatory. The authors describe the development and deployment of an automated diagnosis methodology within Texas Instruments.

Modeling Test Escape Rate as a Function of Multiple Coverages

The Williams and Brown model has long been the gold standard for estimating test escape rate as a function of yield and fault coverage. However, todays test programs have a number of differing test types, often with overlapping failing unit detections. This paper details the development of a method which permits test escape rate predictions based on product yield and multiple overlapping test coverages.