Harlan Cramer

Formation of large-area GaN nanostructures with controlled geometry and morphology using top-down fabrication scheme

This paper details the fabrication of GaN nanoscale structures using deep ultraviolet lithography and inductively coupled plasma (ICP) etching techniques. The authors controlled the geometry (dimensions and shape) and surface morphology of such nanoscale structures through selection of etching parameters. The authors compared seven different chlorine-based etch chemistries: Cl2, Ar, Cl2/N2, Cl2/Ar, Cl2/N2/Ar, Cl2/H2/Ar, and Cl2/He/Ar. The authors found that nitrogen plays a significant role in fabricating high quality etched GaN nanostructures. This paper presents the effects of varying the etch parameters, including gas chemistry, gas flow rate, ICP power, rf power, chamber pressure, and substrate temperature, on the etch characteristics, including etch rate, sidewall angle, anisotropy, mask erosion, and surface roughness. Dominant etch mechanisms in relation to the observed characteristics of the etched features are discussed. Utilizing such methods, the authors demonstrated the fabrication of nanoscale...

Low Loss, High Performance 1-18 GHz SPDT Based on the Novel Super-Lattice Castellated Field Effect Transistor (SLCFET)

A low loss, high isolation, broadband RF switch has been developed using a novel type of field effect transistor structure that exploits the use of a super-lattice structure in combination with a three dimensional, castellated gate to achieve excellent RF switch performance. Using an AlGaN/GaN super-lattice epitaxial layer, this Super-Lattice Castellated Field Effect Transistor (SLCFET) was used to build 1-18 GHz SPDT RF switches. Measured insertion loss of the SPDT at 10 GHz was -0.4 dB, with -35 dB of isolation and -23 dB of return loss, along with a measured linearity OIP3 value 62 dBm and a P0.1dB of 34 dBm.

The Super-Lattice Castellated Field Effect Transistor (SLCFET): A novel high performance Transistor topology ideal for RF switching

NGES reports the development of a novel transistor structure based on a GaN super-lattice channel with a 3D gate, named the SLCFET (Super-Lattice Castellated Field Effect Transistor). Transistor measurements provided median values of I_MAX>2.7 A/mm, V_PINCH = -8V, with R_ON=0.41 Ω-mm and C_OFF=0.19 pF/mm, for an RF switch FOM of F_CO=2.1 THz.

Realization of vertically-aligned GaN n-p core-shell nanoscale structures using top-down fabrication

Vertically aligned core-shell p-n nanostructures are technologically significant due to their potential applications in a variety of devices such as light-emitting diodes, laser diodes, photodetectors, and solar cells. Such structures developed in III-Nitride material system are expected to increase device efficiency, partially due to mitigating detrimental effects of spontaneous electrical polarization. Despite significant progress in the synthesis of nitride core-sell nanostructures using both bottom-up and top-down paradigms, fabrication of large arrays of these nanostructures with controlled morphology, orientation, dopant incorporation, and site-specific nucleation is still a challenge. One of the most challenging aspects of making high quality GaN nanopillar arrays using top-down approach is to design an etching protocol for producing high-aspect ratio structures while inducing minimal damage to the sidewalls and preventing the etch-mask erosion.[1]

Optimizing performance of Super-Lattice Castellated Field Effect Transistors

High performance RF switch components are vital for the successful implementation of a variety of system architectures, ranging from phased array radars and multi-function sensors to the wireless components of mobile phones and consumer electronics. FET based RF switches offer low power consumption, less demanding control biasing networks and fast switching capabilities compared to both PiN and RF MEMS technologies. However, many of these switch technologies, including those based on Si CMOS [1], GaAs pHEMT [2], or InP [3] and GaN HEMTs [4] have reported substantially higher insertion losses than the PiN diode and RF MEMS technologies. With this in mind, Northrop Grumman has recently introduced a novel field effect transistor structure called the Super-Lattice Castellated Field Effect Transistor, or SLCFET, that combines the advantages of FET-based switches with the performance of MEMS [5]. However, this is a new transistor structure that creates challenges for device design, especially with regard to managing electric fields for high breakdown voltage. This paper will discuss some of the challenges, tradeoffs, and techniques for optimizing the SLCFET device performance.

Design and process related MIM cap reliability improvement

Abstract A root cause failure investigation was performed on anomalous (early) MIM capacitor failures on an HBT MMIC process. These failures were only observed on capacitors in the actual MMICs; process control monitor (PCM) capacitors were nominal. Multiple failure analysis techniques were employed to determine the most probable root cause of the early failures. The root cause was determined to be etching of the capacitor dielectric by a chemical used in the MMIC fabrication process, at a step after the capacitors themselves were fully built. It was determined that only CAD layouts with certain features were susceptible to the etching. These features were not present on the PCM capacitors. A design based corrective action was recommended to eliminate the failure mechanism. The effectiveness of the corrective actions was verified with several designed processing experiments. These experiments also demonstrated that the failure rate of the faulty parts increased with the time (even if the parts were not in operation). Finally, the experiments showed that the reliability of a nominal capacitor with a BCB layer on top was better than that of an identical capacitor without the BCB layer. Capacitor reliability model For the sake of completeness, the following discussion on ramped voltage TDDB testing of capacitors is included. In this work, ramped voltage data was not used to predict capacitor lifetimes, but it was used to quantitatively compare capacitor reliability by plotting percent cumulative failure versus failure voltage. Normally, destructive ramped voltage testing and the linear field model are employed in order to estimate the lifetime of capacitors. This method has been described in detail elsewhere for intrinsic capacitors (Cramer et al. [1] , [2] , [3] ). It is generally assumed that defects on or in the capacitor bottom plate or in dielectric itself causes a localized thinning of the dielectric which shortens the intrinsic lifetime of the capacitor, as illustrated in Fig. 2. Extrinsic capacitors require a refinement of the Nominal Thickness Method to the Effective Thickness Method. Typically, plots of percent cumulative failure versus failure voltage will be transformed into plots of percent cumulative failure versus lifetime via the above equations. The shapes of these two plots are nearly identical, only the values on the abscissa are changed from (linear) voltage to (logarithmic) lifetime. Since, in this work, the effort was directed at root cause determination of anomalous failures rather than predictions of expected lifetimes, the linear field model was never employed and the data was always plotted as a function of failure voltage.

Optimization and shape control of GaN nanopillars fabricated by inductively coupled plasma etching

We report the systematic etching profile of GaN nano pillar structures using inductively coupled plasma (ICP) etching techniques. We were able to control the side wall angle, shape and dimension of such nanoscale structures by carefully selecting the etching parameters. We present the effects of variations of the etch parameters, such as ICP power, RF power, chamber pressure, and substrate temperature on the etch characteristics, such as etch rate, sidewall angle, anisotropy, mask erosion, and surface roughness. Utilizing such methods, we demonstrated the fabrication of nanoscale structures with designed shapes and dimensions over large area. Nanocolumns with diameter of 120 nm and height of 1.6 μm with sidewall angle of 86° (90° represent a vertical sidewall) were fabricated. Nanocones with tip diameter of 30 nm and height of 1.6 μm with sidewall angle of 70° were demonstrated. The structures produced by such top-down method could potentially be used in light-emitting diodes, laser diodes, photodetectors, vertical transistors, fieldemitters, and photovoltaic devices.