Karen Renaldo

Low Loss, High Performance 1-18 GHz SPDT Based on the Novel Super-Lattice Castellated Field Effect Transistor (SLCFET)

A low loss, high isolation, broadband RF switch has been developed using a novel type of field effect transistor structure that exploits the use of a super-lattice structure in combination with a three dimensional, castellated gate to achieve excellent RF switch performance. Using an AlGaN/GaN super-lattice epitaxial layer, this Super-Lattice Castellated Field Effect Transistor (SLCFET) was used to build 1-18 GHz SPDT RF switches. Measured insertion loss of the SPDT at 10 GHz was -0.4 dB, with -35 dB of isolation and -23 dB of return loss, along with a measured linearity OIP3 value 62 dBm and a P0.1dB of 34 dBm.

The Super-Lattice Castellated Field Effect Transistor (SLCFET): A novel high performance Transistor topology ideal for RF switching

NGES reports the development of a novel transistor structure based on a GaN super-lattice channel with a 3D gate, named the SLCFET (Super-Lattice Castellated Field Effect Transistor). Transistor measurements provided median values of I_MAX>2.7 A/mm, V_PINCH = -8V, with R_ON=0.41 Ω-mm and C_OFF=0.19 pF/mm, for an RF switch FOM of F_CO=2.1 THz.

High-Performance SLCFETs for Switched Filter Applications

FET-based switched filters do not occupy a large space in the literature due to the high loss of the switches relative to other technologies. The Super-Lattice Castellated Field Effect Transistor (SLCFET) is a low loss, high isolation, broadband RF switch that meets this need. A 4 channel tunable band pass filter employing SLCFET switches in a splitter/combiner network was fabricated in order to demonstrate the enabling capability of the SLCFET for this application. Each filter state employed a novel, high-Q LC circuit. The insertion loss of the MMIC passbands was around -6.5 dB, of which -1.3 dB was attributable to the six Single Pole Double Throw (SPDT) switches in the network. Breakout SPDTs were measured from 0.5 to 25 GHz. Measured insertion loss at 18 GHz was -0.41 ± 0.1 dB and isolation was -28.8 ± 0.1 dB, for 35 SPDTs on the wafer.

Optimizing performance of Super-Lattice Castellated Field Effect Transistors

High performance RF switch components are vital for the successful implementation of a variety of system architectures, ranging from phased array radars and multi-function sensors to the wireless components of mobile phones and consumer electronics. FET based RF switches offer low power consumption, less demanding control biasing networks and fast switching capabilities compared to both PiN and RF MEMS technologies. However, many of these switch technologies, including those based on Si CMOS [1], GaAs pHEMT [2], or InP [3] and GaN HEMTs [4] have reported substantially higher insertion losses than the PiN diode and RF MEMS technologies. With this in mind, Northrop Grumman has recently introduced a novel field effect transistor structure called the Super-Lattice Castellated Field Effect Transistor, or SLCFET, that combines the advantages of FET-based switches with the performance of MEMS [5]. However, this is a new transistor structure that creates challenges for device design, especially with regard to managing electric fields for high breakdown voltage. This paper will discuss some of the challenges, tradeoffs, and techniques for optimizing the SLCFET device performance.