Justin Parke

Low Loss, High Performance 1-18 GHz SPDT Based on the Novel Super-Lattice Castellated Field Effect Transistor (SLCFET)

A low loss, high isolation, broadband RF switch has been developed using a novel type of field effect transistor structure that exploits the use of a super-lattice structure in combination with a three dimensional, castellated gate to achieve excellent RF switch performance. Using an AlGaN/GaN super-lattice epitaxial layer, this Super-Lattice Castellated Field Effect Transistor (SLCFET) was used to build 1-18 GHz SPDT RF switches. Measured insertion loss of the SPDT at 10 GHz was -0.4 dB, with -35 dB of isolation and -23 dB of return loss, along with a measured linearity OIP3 value 62 dBm and a P0.1dB of 34 dBm.

The Super-Lattice Castellated Field Effect Transistor (SLCFET): A novel high performance Transistor topology ideal for RF switching

NGES reports the development of a novel transistor structure based on a GaN super-lattice channel with a 3D gate, named the SLCFET (Super-Lattice Castellated Field Effect Transistor). Transistor measurements provided median values of I_MAX>2.7 A/mm, V_PINCH = -8V, with R_ON=0.41 Ω-mm and C_OFF=0.19 pF/mm, for an RF switch FOM of F_CO=2.1 THz.

Micromachined sapphire GHz lateral overtone bulk acoustic resonators transduced by aluminum nitride

This paper introduces a new class of piezoelectric-transduced bulk acoustic wave resonators formed by a micro-machined c-plane sapphire (Al2O3) membrane (~750 nm). The thin film sapphire (TFS) is fully suspended in air and made to vibrate in the GHz range by a sputtered aluminum nitride (AlN) film. For the first time, the realization of the TFS is achieved via a layer transfer process from a single crystal c-plane sapphire wafer. In order to demonstrate the superior intrinsic material quality of the sapphire membrane, a lateral overtone bulk acoustic resonator (LOBAR) configuration, recently introduced by our group, was employed. The LOBAR is engineered to minimize the effects of mechanical energy dissipation and extract the ultimate limit set by phonon-phonon dissipation in the TFS. In addition to the conventional rectangular design, an annular LOBAR geometry is introduced in this paper. This design permits to lower the device impedance (~3k Ω), while attaining a high quality factor (Q). The measured responses exhibit f·Q of 4.1·1012 Hz and 4.6·1012 Hz at 1 and 2 GHz, respectively in the annular configuration with a 9% of transducer to sapphire coverage ratio. The conventional rectangular LOBAR with coverage ratio of 0.57% exhibits a Q of 5,440 at 2.8 GHz, which translates to the highest f·Q (1.53·1013 Hz) ever reported for AlN-based suspended resonators.

Advances in the Super-Lattice Castellated Field Effect Transistor (SLCFET) for wideband low loss RF switching applications

The Super-Lattice Castellated Field Effect Transistor (SLCFET) uses a super-lattice in the channel region to form multiple parallel current paths in conjunction with castellations etched into that super-lattice to provide a sidewall gate structure. The sidewall gate permits the gate applied electric field to penetrate between the parallel 2DEG layers, allowing the carriers to be depleted out prior to avalanche breakdown within the material, as would occur with a conventional gate structure. Using an AlGaN/GaN super-lattice, we report on this method as a way to scale RF switch performance, decreasing ON resistance without significantly increasing OFF capacitance, with a median measured ON resistance of 0.38 Ω-mm and a median measured OFF capacitance of 0.21 pF/mm, leading to an RF switch figure of merit, FCO=2.0 THz. 90/10 and 10/90 fall and rise times for the SLCFET have been measured to be faster than 100 nsec, while the RF power handling for a series SLCFET has been measured at 10 GHz to be greater than 10 W without loss compression. Wideband SPDT RF switch performance over a 0.5-20 GHz bandwidth with <;|-0.3| dB of insertion loss and >|-30| dB of isolation has been achieved.

High-Performance SLCFETs for Switched Filter Applications

FET-based switched filters do not occupy a large space in the literature due to the high loss of the switches relative to other technologies. The Super-Lattice Castellated Field Effect Transistor (SLCFET) is a low loss, high isolation, broadband RF switch that meets this need. A 4 channel tunable band pass filter employing SLCFET switches in a splitter/combiner network was fabricated in order to demonstrate the enabling capability of the SLCFET for this application. Each filter state employed a novel, high-Q LC circuit. The insertion loss of the MMIC passbands was around -6.5 dB, of which -1.3 dB was attributable to the six Single Pole Double Throw (SPDT) switches in the network. Breakout SPDTs were measured from 0.5 to 25 GHz. Measured insertion loss at 18 GHz was -0.41 ± 0.1 dB and isolation was -28.8 ± 0.1 dB, for 35 SPDTs on the wafer.

Optimizing performance of Super-Lattice Castellated Field Effect Transistors

High performance RF switch components are vital for the successful implementation of a variety of system architectures, ranging from phased array radars and multi-function sensors to the wireless components of mobile phones and consumer electronics. FET based RF switches offer low power consumption, less demanding control biasing networks and fast switching capabilities compared to both PiN and RF MEMS technologies. However, many of these switch technologies, including those based on Si CMOS [1], GaAs pHEMT [2], or InP [3] and GaN HEMTs [4] have reported substantially higher insertion losses than the PiN diode and RF MEMS technologies. With this in mind, Northrop Grumman has recently introduced a novel field effect transistor structure called the Super-Lattice Castellated Field Effect Transistor, or SLCFET, that combines the advantages of FET-based switches with the performance of MEMS [5]. However, this is a new transistor structure that creates challenges for device design, especially with regard to managing electric fields for high breakdown voltage. This paper will discuss some of the challenges, tradeoffs, and techniques for optimizing the SLCFET device performance.

Design and process related MIM cap reliability improvement

Abstract A root cause failure investigation was performed on anomalous (early) MIM capacitor failures on an HBT MMIC process. These failures were only observed on capacitors in the actual MMICs; process control monitor (PCM) capacitors were nominal. Multiple failure analysis techniques were employed to determine the most probable root cause of the early failures. The root cause was determined to be etching of the capacitor dielectric by a chemical used in the MMIC fabrication process, at a step after the capacitors themselves were fully built. It was determined that only CAD layouts with certain features were susceptible to the etching. These features were not present on the PCM capacitors. A design based corrective action was recommended to eliminate the failure mechanism. The effectiveness of the corrective actions was verified with several designed processing experiments. These experiments also demonstrated that the failure rate of the faulty parts increased with the time (even if the parts were not in operation). Finally, the experiments showed that the reliability of a nominal capacitor with a BCB layer on top was better than that of an identical capacitor without the BCB layer. Capacitor reliability model For the sake of completeness, the following discussion on ramped voltage TDDB testing of capacitors is included. In this work, ramped voltage data was not used to predict capacitor lifetimes, but it was used to quantitatively compare capacitor reliability by plotting percent cumulative failure versus failure voltage. Normally, destructive ramped voltage testing and the linear field model are employed in order to estimate the lifetime of capacitors. This method has been described in detail elsewhere for intrinsic capacitors (Cramer et al. [1] , [2] , [3] ). It is generally assumed that defects on or in the capacitor bottom plate or in dielectric itself causes a localized thinning of the dielectric which shortens the intrinsic lifetime of the capacitor, as illustrated in Fig. 2. Extrinsic capacitors require a refinement of the Nominal Thickness Method to the Effective Thickness Method. Typically, plots of percent cumulative failure versus failure voltage will be transformed into plots of percent cumulative failure versus lifetime via the above equations. The shapes of these two plots are nearly identical, only the values on the abscissa are changed from (linear) voltage to (logarithmic) lifetime. Since, in this work, the effort was directed at root cause determination of anomalous failures rather than predictions of expected lifetimes, the linear field model was never employed and the data was always plotted as a function of failure voltage.