Isamu Hayashi

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/m logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-/spl mu/W data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory

A twin-transistor random access memory (TTRAM) can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. Enhanced TTRAM (ET2RAM) applies the actively body-bias control technique to realize the low voltage array operation, and never require the negative voltage source. The ET2RAM can realize both 263 MHz at 0.8 V and 10.2 mW at 0.5 V random-cycle operation, higher cell efficiency, and process scalability. It also provides the simple control method suitable for the unified macro for system-level power management SoC with keeping the merits of TTRAM as CMOS compatibility

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI

We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2Mb test device has been fabricated on 130nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80°C. TTRAM process is compatible with the conventional SOI-CMOS and never requires any additional processes. A 6.1 ns row-access time is achieved and 250 MHz operation can be realized by using 2 bank 8 b-burst mode.

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs

Several high-density SOI memory technologies utilizing the body floating effects have been proposed. Conditions needed for SoC memory IPs for many kinds of applications are not only performance but also suitability for platform technologies. We had reported TTRAM (Twin Transistor RAM) and (Enhanced TTRAM) which are high-density capacitorless SOI-CMOS compatible memory IPs. A platform design methodology becomes the mainstream, providing QTAT and low-cost design. Now, we have upgraded the with application-required functions called scalable TTRAM. This memory IP can be applied to many kinds of applications using the verify control technique with compact actively body-bias controlled (ABC) sense amplifier, and the unique test mode functions have also been proposed for practical usage. The test chip of 4 Mbit macro fabricated with 90 nm standard SOI CMOS achieves performance of 263 MHz high-speed random access, 79 mW/4 Mb lower active power dissipation, 453 MHz data transfer of page/burst mode and lower stand-by current mode of 5 s data retention time. The scalable TTRAM can play the role of on-chip SoC memory IPs, for example, in consumer, mobile, and MPU/game applications.

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture

An asynchronous transfer mode (ATM) switch chip set, which employs a shared multibuffer architecture, and its control method are described. This switch architecture features multiple-buffer memories located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the number of stored ATM cells in each buffer memory, these buffer memories can be treated as a single large shared buffer memory. Thus, buffers are used efficiently and the cell loss ratio is reduced to a minimum. Furthermore, no multiplexing or demultiplexing is required to store and restore the ATM cells by virtue of parallel access to the buffer memories via the crosspoint switches. Access time for the buffer memory is thus greatly reduced. This feature enables high-speed switch operation. A three-VLSI chip set using 0.8- mu m BiCMOS process technology has been developed. Four aligner LSIs, nine bit-sliced buffer-switch LSIs, and one control LSI are combined to create a 622-Mb/s 8*8 ATM switching system that operates at 78 MHz. In the switch fabric, 155-Mb/s ATM cells can also be switched on the 622-Mb/s port using time-division multiplexing. >

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

An 18-Mb full ternary CAM with low-voltage matchline sensing scheme (LVMLSS) is designed and fabricated in 65-nm bulk CMOS process. LVMLSS has three key techniques: voltage down converter, differential sense amplifier with matchline isolation, and reference voltage generation scheme. With these techniques, LVMLSS can reduce the dynamic power consumption of matchlines to 33% compared with conventional one and realizes 42% fast match-line sensing. At 1.0-V typical supply voltage, 250-MHz search frequency is achieved. The power consumption of fully paralleled search operation at 250 MHz is 9.3 W, which is 66% smaller than previous work. This work has realized high-speed, low-power, and robust large-scale TCAM. We believe that this work will greatly contribute to reducing the power of network systems.

A 312MHz 16Mb random-cycle embedded DRAM macro with 73/spl mu/W power-down mode for mobile applications

An embedded DRAM macro with self-adjustable timing control and a power-down data retention scheme is described. A 16Mb test chip is fabricated in a 0.13/spl mu/m low-power process and it achieves 312MHz random cycle operation. Data retention power is 73/spl mu/W, which is 5% compared to a conventional one.

13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM

The number of IPv4 routing table entries was around 460k in 2012 and is growing at a rate of 10% per year. The continuing increase of network-connected devices risks depletion of IPv4 addresses. As for IPv6, the number of routing-table entries is about to reach 16k with a rapid annual growth rate of 90%. This growth trend will continue in the Internet-of-Things era. In growing network applications with large amounts of traffic, there is a demand for routers and switches capable of packet processing for applications such as forwarding, quality of service, classification and access control. Fully parallel ternary content-addressable memories (TCAMs) are the key devices to handle the large number of routes in the lookup table with high-throughput low-latency header processing [1-6]. Realizing both high-density (high-capacity) and high-speed search operation is a challenge due to high power consumption and diminishing signal integrity for search operations. Process scaling is important to achieve a high-density high-performance TCAM, but it incurs the decrease of operating margin caused by threshold-voltage variation. This paper presents a 400MHz 4-paralleled search-operation 80Mb TCAM test-chip in a 28nm process that can accommodate 1M entries. This chip has three key features: flexible search mode, row and column shift redundancy, and search omission with valid-bit. With flexible search mode, the TCAM can be adapted to both IPv4 and IPv6.

A Configurable Enhanced T/sup 2/RAM Macro for System-Level Power Management Unified Memory

TTRAM can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. The enhanced TTRAM (ET2RAM) can solve these issues and the key technologies provide 0.5V memory operation, compact and higher sensitivity sense amplifier, and programmable multi-bank array