Taeko Ikarashi

Dual workfunction Ni-Silicide/HfSiON gate stacks by phase-controlled full-silicidation (PC-FUSI) technique for 45nm-node LSTP and LOP devices

We present a new threshold-voltage (Vth) control technique for fully-silicided (FUSI) metal/high-k gate stacks which are suitable for 45nm-node LOP and LSTP CMOS. The key is the phase control of FUSI Ni-silicide by changing Ni film thickness prior to silicidation anneal. As a result, Ni/sub 3/Si and NiSi/sub 2/ are formed whose effective workfunctions (WFs) on HfSiON are found to be 4.8eV and 4.4eV, respectively, being largely displaced from Si-midgap by /spl plusmn/0.2eV. Meanwhile, the dopant segregation method, known to be successful in Vth-control of NiSi on SiO/sub 2/, did not work on HfSiON. With Ni/sub 3/Si-PMOS and NiSi/sub 2/-NMOS transistors, a wide range of Vth-tuning is achieved coping with both LSTP and LOP requirements. At the same time, leakage suppression merit is better than the 45nm-node targets at electrical thickness (Tinv) around 2.0 nm. Also, our phase-controlled fully silicided (PC-FUSI) devices show excellent mobility characteristics.

Facet formation mechanism of silicon selective epitaxial layer by Si ultrahigh vacuum chemical vapor deposition

Abstract Faceting morphology of Si layers selectively grown at different growth times has been investigated to study facet formation mechanism. The epitaxial layers have been grown on Si(100) patterned substrates using Si 2 H 6 with an ultrahigh vacuum chemical vapor deposition (UHV-CVD) system. It is found that the faceting process consists of two stages. One is the initial stage of faceting, when the faceting planes are generated. In this stage, the faceting morphology changes from (311) faceting to the faceting composed of (311) and (111) planes with increasing layer thickness, because the growth rates of the faceting planes are not constant in these small areas due to the surface Si migration. The morphology transition can be simulated by free energy considerations. After the faceting plane becomes large enough to have a constant growth rate, a second stage follows when the faceting planes have developed due to the difference in growth rate between the (100) plane and each faceting plane.

Infrared studies of transition layers at SiO2/Si interface

We investigated transition layers at the interface of the thin SiO2 film successively etched back by diluted HF, using infrared reflection-absorption spectroscopy. The etching rate of the oxide film reveals that there is a Si-rich transition layer within 0.6 nm of the interface. However, frequency shift in the longitudinal optical phonon due to Si-O-Si asymmetric stretching toward lower wave numbers takes place less than 1.5 nm from the interface. We propose a model in which the transition layer is assumed to be Si-rich suboxide layers caused by the compositional roughness of the SiO2/Si interface. Through estimating the phonon frequencies which depend on the composition of the suboxide structure in this model, we found that the phonon frequency apparently starts to shift at around 1.5 nm from the interface, even if there are suboxide-rich layers within 0.6 nm, which can be caused by 1–2 monolayers of roughness.

Hemispherical grained Si formation on in-situ phosphorus doped amorphous-Si electrode for 256 Mb DRAM's capacitor

The cylindrical capacitor structure with hemispherical grained-Si (HSG-Si) described here reliably achieves a cell capacitance of 30 fF in a 0.4 /spl mu/m-high storage electrode with a cell area of a 0.72 /spl mu/m/sup 2/ for 256 Mbit dynamic random access memory. An HSG-Si formation technology using Si/sub 2/H/sub 6/-molecule irradiation and annealing enables control of the grain density and grain size of HSG-Si fabricated selectively on the whole surface of phosphorus-doped amorphous Si cylindrical electrodes. >

An advanced technique for fabricating hemispherical-grained (HSG) silicon storage electrodes

In this new fabrication technology for high-density DRAMs, an electrode with even-surface amorphous-silicon is changed to one with uneven-surface hemispherical-grained Si (HSG-Si). This fabrication method consists of easily controllable processes: formation of smooth amorphous Si electrodes by low-pressure chemical vapor deposition followed by removal of native oxide and high-vacuum annealing. This annealing process can form HSG-Si covering the entire surface of all types of storage electrodes, including side-wall surfaces which had previously been dry-etched. The resulting storage electrode with HSG-Si can store 1.8 times as much charge as can be stored on an electrode without HSG-Si. Such an increase makes it possible to reduce the height of storage electrodes. This technique is applicable to the fabrication of high-density DRAMs. >

High mobility MISFET with low trapped charge in HfSiO films

MISFETs with HfSiO (EOT:1.8 nm) gate insulator have been reached high Ion (95%) and low gate leakage current (1/100) against SiO/sub 2/ gate film. This was achieved by the suppression of the remote Coulomb scattering, caused by the electron traps in the HfSiO gate stack. It was experimentally confirmed that less than 3/spl times/10/sup 12/ C/cm/sup 2/ electron trap level is required to get high mobility.

BONDING CONFIGURATIONS OF NITROGEN ABSORPTION PEAK AT 960 CM-1 IN SILICON OXYNITRIDE FILMS

We investigated bonding configurations of nitrogen atoms in silicon oxynitride films, resulting in a 960 cm−1 absorption peak, which is a higher frequency than that for Si3N4 (840 cm−1). The 960 cm−1 peak was observed in the films for which an N 1s x-ray photoemission peak was observed with a binding energy of about 398.6 eV, which has been reported as a binding energy associated with the ≡Si–N–Si≡ structure. However, the 960 cm−1 peak was absent in the films for which the N 1s peak was observed at about 397.8 eV, being close to the binding energy associated with the Si3≡N structure. We conclude that the absorption peak at 960 cm−1 arises from the ≡Si–N–Si≡ structure of doubly bonded N atoms with two Si atoms, not affected by any oxygen atoms.

Formation mechanism of interfacial Si–oxide layers during postannealing of Ta2O5/Si

The Si–O–Si bonds formed at the Ta2O5/Si interface by annealing were investigated by using Fourier transform infrared absorption spectroscopy. The Ta2O5 thin films deposited on Si substrates were annealed in different ambient (H2O, O2, and N2) at temperatures between 500 and 800 °C. When annealing is done in H2O, the interfacial silicon–oxide grows very rapidly, because the oxidation species can easily diffuse through Ta2O5 films, and because the Si–O formation is controlled by the diffusion of H2O in the interfacial layer. When annealing is done in O2, the oxidation species can also easily diffuse through Ta2O5, but not through the interfacial layer. The interfacial layer is formed by a reaction between Ta2O5 and Si even if the annealing ambient does not contain oxidation species, as is the case when annealing is done in N2. We conclude that the Si–O formation during postannealing in O2 and N2 is controlled by the diffusion of the Si from the substrate through the interfacial layer with an activation ene...

A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes

For 90 nm node poly-Si gated MISFETs with HfSiO (1.8 nm) insulator, a nearly symmetrical set of Vths for NFET and PFET: (0.38 V and -0.46 V, respectively) have been realized for low power device operation. The key technology is the suppression of Vth instability in PFETs arising from oxidation of the poly-Si/HfSiO interface, combined with channel engineering for the PFET. Our poly-Si/HfSiO gate-stacked CMOSFETs realize low I/sub off/ (N/PFET: 4.8/3.6 pA//spl mu/m) and high I/sub on/ (N/PFET: 469/140 /spl mu/A//spl mu/m) at V/sub DD/=1.2 V. Further, for SRAM cell using this CMOS, normal operation has been achieved.

Infrared studies of silicon oxide formation in silicon wafers implanted with oxygen

The formation process of buried oxide in low-dose oxygen-implanted wafers was investigated using Fourier-transform infrared absorption spectroscopy. In the wafers as-implanted with oxygen, the peak position of the Si–O–Si asymmetric stretching mode was observed to be lower in wave numbers for the lower dose samples, in which the oxygen atoms are buried as substoichiometric silicon oxide with small stress. Therefore, we conclude that the frequency shift is not caused by compressive stress but by the substoichiometry of the buried oxide. After annealing at over 600 °C, the buried oxide starts to form stoichiometric silicon dioxide, and completes it at over 1200 °C. However, we also found that some amount of oxygen atoms diffuse out of the wafer at a temperature over 1000 °C.