Hiromu Yamaguchi

Barrier layers for realization of high capacitance density in SrTiO3 thin‐film capacitor on silicon

High dielectric constant SrTiO3 thin films were sputter deposited on barrier layers/Si substrate to fabricate a capacitor for dynamic random access memories. Dielectric constant (er) values of 140–210 were achieved for the 150‐nm‐thick SrTiO3 films using a Pt/Ti or Pt/Ta double‐layer barrier. In the Pt(50 nm)/Ti(10 nm), Pt(50 nm)/Ti(50 nm), and Pt(50 nm)/Ta(10 nm) barrier, effective er decreased by annealing in the temperature range between 450 and 550 °C, where the interdiffusion of Pt and Si was confirmed by x‐ray diffraction analysis and cross‐sectional transmission electron microscopy. In the Pt(50 nm)/Ta barrier, increase of the Ta thickness from 10 to 50 nm brought out a remarkable improvement of endurance to high‐temperature annealing. That is, in the Pt(50 nm)/Ta(50 nm) barrier, large er value (∼200) was maintained even with annealing at up to 700 °C.

Structural and electrical characterization of SrTiO3 thin films prepared by metal organic chemical vapor deposition

SrTiO3 thin films were prepared on Si and Pt/TaOx/Si substrates by Sr(DPM)2/Ti(i-OC3H7)4/O2/Ar chemical vapor deposition (CVD), using a simple vaporizing-and-transport source delivery system. A thickness uniformity of ±5.6% and a composition uniformity of ±2.7% were obtained. The dielectric constant was 210 for 110 nm thick SrTiO3 films (Sr/(Sr+Ti)=0.5) annealed at 600°C for 2 hours. An SiO2 equivalent thickness of 1.1 nm was obtained for 40 nm thick SrTiO3 films, and leakage current densities were 6×10-8 A/cm2 at 1.0 V and 5×10-7 A/cm2 at 1.65 V. The structural and electrical properties were affected by the film composition.

Reactive Coevaporation Synthesis and Characterization of SrTiO3 Thin Films

SrTiO3 thin films were prepared by the reactive coevaporation method, where the Ti and Sr metals were evaporated in oxygen ambient with an E-gun and K-cell, respectively. A uniform depth profile in composition was achieved by altering the Ti evaporation rate according to the Sr evaporation rate change. A typical dielectric constant of 170 was measured on films of 75 nm in thickness. The in-situ annealing in oxygen plasma reduced the leakage current.

Chemical Vapor Deposition of ( Ba , Sr ) TiO3

SrTiO 3 and (Ba, Sr)TiO 3 thin films were fabricated on Si and Pt/TaO 2 /Si substrates by chemical vapor deposition (CVD) using Sr(DPM) 2 , Ba(DPM) 2 , Ti(O-i-C 3 H 7 ) 4 , and O 2 where DPM is dipivaloylmethanate or formally 2,2,6,6-tetramethyl-3,5-heptanedionate. The deposition system was operated in both thermal CVD mode and electron cyclotron resonance (ECR) plasma CVD mode. Variations in individual Sr and Ti deposition rates with differing deposition conditions were investigated. The SrTiO 3 and (Ba, Sr)TiO 3 films were characterized with a view to discussing the step-coverage, crystal structure, and electrical properties. The step-coverage over the 300 nm wide SiO 2 lines, with 500 nm height and 500 nm spacing, was 30 to 40%. The 40 to 100 nm SrTiO 3 films, through the postdeposition annealing process, showed dielectric constants >140 with a leakage current density level <10 -7 A/cm at 1 V. The prospects for applying the CVD (Ba, Sr)TiO 3 films to giga-bit dynamic random access memory storage capacitors are discussed

A stacked capacitor technology with ECR plasma MOCVD (Ba,Sr)TiO/sub 3/ and RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO/sub 3/ thin films is described, The four-layer RuO/sub 2//Ru/TiN/TiSi/sub x/, storage node configuration allows 500/spl deg/C processing and fine-patterning down to the 0.20 /spl mu/m size by electron beam lithography and reactive ion etching. Good insulating (Ba/sub 0.4/Sr/sub 0.6/)TiO/sub 3/ (BST) films with an SiO/sub 2/ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1/spl times/10/sup -/6 A/cm/sup 2/ at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 /spl mu/m size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 /spl mu/m/sup 2/ with only the 0.3 /spl mu/m high-storage electrodes.

Interface Structure and Dielectric Properties of SrTiO 3 Thin Film Sputter-Deposited onto Si Substrates

SrTiO 3 thin film preparation onto Si substrates using RF magnetron sputtering has been studied for a high capacitance density required for the next generation of LSIs. Structural and chemical analysis on the interface between SrTiO 3 film and Si was carried out with cross-sectional TEM, EDX, and AES. Dielectric properties were measured on AuTi/SrTiO 3 /Si/Ti/Au capacitors. The as-grown dielectric films on Si were analyzed and found to consist of three layers; SiO 2 , amorphous SrTiO 3 and crystalline SrTiO 3 , from interface toward film surface. By annealing at 600 °C, the amorphous SrTiO 3 layer was recrystallized, and consequently the capacitance value increased. A typical specific capacitance was 4.7 fF/μm 2 and the leakage current was in the order of 10 −8 A/cm 2 , for 180 nm thick SrTiO 3 film. The dielectric constant decreased from 147 to 56 with decreasing SrTiO 3 film thickness from 480 nm to 80 nm. This is due to the low dielectric constant SiO 2 layer (e=3.9) at the interface. From the film thickness dependence of the e value, the SiO 2 layer thickness was calculated to be 3.9 nm, which agreed well with the value directly observed in the TEM. To avoid SiO 2 layer formation, barrier layers between SrTiO 3 and Si have been studied. Among various refractory and noble metals, RuSi and a multi-layer of Pt/Ti have been found to be promising candidates for the barrier material. When RuSi film or Pt/Ti film was formed between SrTiO 3 film and Si substrate, dielectric constant of about 190 was obtained in dependent of the SrTiO 3 film thickness in the range of 80–250 nm. Analysis on the barrier layers was performed by means of RBS, XPS and XRD.

SrTiO3 thin films by mocvd for 1 gbit DRAM application

Abstract Three important aspects of the preparation of SrTiO3 thin films by MOCVD are discussed in detail in view of the application of these films as the capacitor dielectric of Gbit-scale DRAMs: CVD reactions in the Sr(DPM)2-Ti(i-OC3H7)4-O2 system, step coverage and relations between microstructure and electrical properties. The effect of the substrate temperature on the Sr and Ti deposition rates was first investigated for thermal and ECR CVD SrTiO3 films. SrO and TiO2 deposition by thermal CVD above 550°C were found to be controlled by the surface reaction and gas transport, respectively, whereas both SrO and TiO2 deposition are controlled by gas transport for ECR CVD at 450 to 600°C. The influence of the Sr and Ti deposition regimes on the step coverage of SrO, TiO2 and SrTiO3 were then assessed. SrO films prepared by thermal CVD at 600°C exhibited the best step coverage, indicating that a relation exists between reaction controlled deposition and good step coverage. The effect of the film compositio...

Formation mechanism of interfacial Si–oxide layers during postannealing of Ta2O5/Si

The Si–O–Si bonds formed at the Ta2O5/Si interface by annealing were investigated by using Fourier transform infrared absorption spectroscopy. The Ta2O5 thin films deposited on Si substrates were annealed in different ambient (H2O, O2, and N2) at temperatures between 500 and 800 °C. When annealing is done in H2O, the interfacial silicon–oxide grows very rapidly, because the oxidation species can easily diffuse through Ta2O5 films, and because the Si–O formation is controlled by the diffusion of H2O in the interfacial layer. When annealing is done in O2, the oxidation species can also easily diffuse through Ta2O5, but not through the interfacial layer. The interfacial layer is formed by a reaction between Ta2O5 and Si even if the annealing ambient does not contain oxidation species, as is the case when annealing is done in N2. We conclude that the Si–O formation during postannealing in O2 and N2 is controlled by the diffusion of the Si from the substrate through the interfacial layer with an activation ene...

An ECR MOCVD (Ba,Sr)TiO/sub 3/ based stacked capacitor technology with RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gbit-scale DRAMs

A high dielectric constant (Ba,Sr)TiO/sub 3/ [BST] based stacked capacitor with new RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes was developed for Gbit-scale DRAMs. Good insulating BST films with a small t/sub eq/ of 0.65 nm on the electrode sidewalls were obtained by ECR MOCVD. The four-layer storage node allows 500/spl deg/C processing and fine-patterning down to 0.20 /spl mu/m by EB lithography and RIE. A cell capacitance of 25 fF in 0.125 /spl mu/m/sup 2/ is achieved using 0.3 /spl mu/m-high storage electrodes for 1 Gbit DRAMs.

Barrier mechanism of Pt/Ta and Pt/Ti layers for SrTiO3 thin film capacitors on Si

Abstract The barrier effect of Pt/Ta and Pt/Ti has been investigated, when used as bottom electrodes for SrTiO3 thin film capacitors on Si. The Pt/Ta/Si stacks were more stable than the Pt/Ti/Si, both in vacuum and in oxygen annealing. Though the Pt/Ta bilayer was suitable for the SrTiO3 deposition at 400[ddot]C, its resistivity became slightly higher after the deposition at 600[ddot]C, due to Ta layer oxidation during the SrTiO3 deposition. This would result in a contact resistance problem for high density dynamic random access memory application.