Haruki Toda

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond

Circuit techniques for realizing low-voltage and low-power SoCs for 90-nm CMOS technology and beyond are described. A proposed SAFBB (self-adjusted forward body bias techniques), ATC (Asymmetric Three transistor Cell) DRAM, and ADC using an offset can-celing comparator deal with leakage and variability issues for these technologies. A 32-bit adder using SAFBB attained 353-μA at 400-MHz operation at 0.5-V supply voltage, and 1 Mb memory array using ATC DRAM cells achieved 1.5 mA at 50MHz, 0.5 V. The 4-bit ADC attained 2 Gsample/s operation at a supply voltage of 0.9 V.

Performance measurement and improvement of asymmetric three-tr. cell (ATC) DRAM toward 0.3V memory array operation

For a Mb-class embedded memory, asymmetric three-transistor cell (ATC) DRAM has been reported. The memory cell is a non-destructive-read type and the memory array runs at 0.5V, half the voltage of normal peripheral circuits, on a 90nm generic CMOS logic process. A sense amplifier designed for this DRAM is insensitive to input capacitance and can operate with a power supply voltage as low as 0.5V. Through our experiments, we have identified three ways to improve the ATC DRAM. And these improvements enable the sense time to be 6.3ns and refresh power consumption to be 45/spl mu/W with 0.3V memory array voltage by simulation results.