Hironobu Akita

A 333 MHz, 20 mW, 18 ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC (PVR-DAC)

A new Delay Locked Loop (DLL) using a Digital-to-Analog Converter with the Parallel Variable Resister (PVR-DAC) has been developed. The PVR-DAC successfully manages the current controlled-delay element (CCDE) and achieves a fine time-based resolution. The DLL adopting PVR-DAC has been simulated. It realizes a time-based resolution of 18 ps, an operation frequency range of 143 MHz through 333 MHz, with the maximum power consumption of 20 mW at 1.5 V, and also achieves the small circuit area of 0.5 mm/sup 2/.

A novel analog mirror type DLL suitable for low voltage operation with self-calibration method

A new architecture of the analog mirror type DLL has been developed. A dynamic comparator and self-calibration feedback loop are employed. The operation error of less than 50ps is confirmed under the condition of 1.6V supply voltage and 1.4V internal voltage. The proposed circuit is suitable for low-voltage and high-speed applications.