Kenji Tsuchida

A 64Mb MRAM with clamped-reference and adequate-reference schemes

In order to realize a sub-Giga bit scale NVRAM, the novel MRAM based on the spin-transfer-torque (STT) switching has been intensively investigated due to its excellent scalability compared with a conventional magnetic field induce switching MRAM [1]. However, the memory cell size of STT-MRAM reported so far is still over 1µm2, and the memory capacity is limited to 32Mbit even in almost 100mm2 die size [2]. The large cell size is due to the large switching current of MRAM cells. In order to reduce the cell size, we have proposed the perpendicular tunnel magnetoresistance (P-TMR) device, and have confirmed its high potential to achieve lower switching current [3]. In this paper, a 64Mb STTMRAM with the P-TMR device having the circuit techniques to maximize operational margin is described.

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGTs) For ultra high density DRAMs. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGTs connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL. >

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode

A 5-V 4M-word*4-b dynamic RAM (random-access memory) with a 100-MHz serial read/write mode using 0.7- mu m triple-tub CMOS technology is discussed. The RAM utilizes a recently developed STT (stacked trench capacitor) cell which achieved 37 fF in a small cell size of 1.7*3.6 mu m/sup 2/. The STD (sidewall transistor with double-doped drain) structure is used for PMOS-FETs to realize high-speed operation. To ensure MOSFET reliability, the 5-V external supply voltage is converted to a 4-V internal supply voltage by an on-chip voltage converter circuit. An on-chip interleaved circuit and double-input-buffer scheme is used to realize high-speed serial read/write operation. Using an external 5-V power supply, the RAM achieved a 100-MHz serial access cycle, and RAS access time is 70 ns. The typical active current is 120 mA at a 190-ns cycle time. >

New nibbled-page architecture for high-density DRAMs

A nibbled-page architecture which can be used to access all column addresses on the selected row address randomly in units of 8 bits at the 100 Mbit/s data rate is discussed. To realize such high-speed architecture, three key circuit techniques have been developed. An on-chip interleaved circuit has been used for the high-speed serial READ and WRITE operations. Column address prefetch and WE signal prefetch techniques have been introduced to eliminate idle time between 8 bit units. The nibbled-page architecture has been successfully implemented in an experimental 16 Mb DRAM, and 100 Mb/s operation has been achieved. The DRAM with nibbled-page mode is very effective in simplifying the design of high-speed data transfer systems. >

A 33-ns 64-Mb DRAM

A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm/sup 2/ has been fabricated using a 0.4- mu m N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. The asymmetrical stacked-trench capacitor (AST) cells, 0.9 mu m*1.7 mu m each, are laid out in a PMOS centered interdigitated twisted bit-line (PCITBL) scheme that achieves both low noise and high packing density. Three circuit techniques were developed to meet high-speed requirements. Using the preboosted word-line drive-line technique, a bypassed sense-amplifier drive-line scheme, and a quasi-static data transfer technique, a typical RAS access time of 33 ns and a typical column address access time of 15 ns have been achieved. >

4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure

For the first time, 4Gbit density STT-MRAM using perpendicular MTJ in compact cell was successfully demonstrated through the tight distributions for resistance and magnetic properties. This paper includes the results regarding parasitic resistance control process, MTJ process, and MTJ stack engineering. Both of successful 4Gb read and write operations were performed with high TMR, low Ic. This result will brighten the prospect of high-density STT-MRAM.

Improvement of robustness against write disturbance by novel cell design for high density MRAM

A new bit cell designed to have an excellent astroid is presented from the viewpoints of both theory and experiment. The switching mechanism is unique. The robustness against the disturbance of half-selected bits is improved. Its excellent astroid improves thermal stability and has the potential to achieve extremely high density magnetoresistive random access memory (MRAM).

Bit yield improvement by precise control of stray fields from SAF pinned layers for high-density MRAMs

A write-operating window with a 100% functional bit yield was successfully obtained by the control of stray fields from synthetic antiferromagnetic (SAF) pinned layers in conventional magnetic random access memories with rectangular magnetic tunneling junction bits. The stray fields were controlled by a newly developed ion-beam etching technique without causing damage and by a precise setting of the SAF pinned layer thickness, and are balanced with Neel coupling fields. As a result, it was found that symmetric switching astroid curves with no offset were obtained and switching distributions were minimized at the zero offset field.

Design and process integration for high-density, high-speed, and low-power 6F/sup 2/ cross point MRAM cell

A cross point (CP) cell with hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) based in Y. Shimizu et al. (2004). The new CP cell has a potential high density of 6F/sup 2/ and a faster access time than the conventional CP cell. A cell layout design to realize 6F is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 /spl mu/m CMOS technology and 0.24/spl times/0.48 /spl mu/m/sup 2/ magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.

A pseudo multi-bank DRAM with categorized access sequence

A new architecture which realizes the large bandwidth with virtually the same core circuitry as a conventional DRAM is proposed. The improved row block activation scheme combined with a categorized access sequence improves the bandwidth of the DRAM even with the shared sense amplifier scheme. The data efficiency of the random read/write mixed cycle is improved by the proposed delayed write operation, which fills the write to read command gap effectively. The proposed architecture is successfully examined in the 128 Mbit test vehicle fabricated with a 0.15 /spl mu/m CMOS process.