Hazara S. Rathore

Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL

Integration and development of Cu Back-End of Line (BEOL) with PECVD low-k organosilicate glass (OSG, also called SiCOH, carbon-doped oxide, CDO, etc.) for 130 nm and 90 nm CMOS technologies has been reported by a number of institutions. Here we report on a Cu/SiCOH technology which has similarities, but also enhanced integration and reliability characteristics while preserving the R and C performance levels. These enhancements have led to excellent reliability results reported here, and are expected to increase the robustness to high-volume manufacturing and extendibility to next-generation smaller dimensions. The SiCOH and cap mechanical, chemical, and electrical strengths are increased, as well as associated interfacial adhesions. These combine with an optimized Cu metallization. As chip-package reliability is most at risk for low-k dielectrics, improvements have been brought into the BEOL level structure, the kerf design, and in some cases new packaging materials. When combined with the dielectric material and interface improvements, redundancy exists in the protection against potential chip-packaging failures. No failures occur in the full rounds of chip-package reliability stress testing done here on multiple wirebond and flip-chip packages. These packaging and other reliability results are presented, including BEOL-specific tests [electromigration (E-M), stress-migration (S-M), time-dependent dielectric breakdown (TDDB), thermal cycling (T/C)], environmental [temperature-humidity-bias (THB)], and functional stressing of product modules. The stress criteria and results exceeded JEDEC standards. All Cu/SiCOH tests passed at the same levels as our concurrent 90 nm Cu/SiOF technology.

Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology

We report a comprehensive characterization of a 90 nm CMOS technology with Cu/SiCOH low-k interconnect BEOL. Significant material and integration engineering have led to the highest reliability, without degrading the performance expected from low-k. Results are presented on every aspect of BEOL and chip-package reliability, yields, low-k film parameters, BEOL capacitances and circuit delays on functional chips. All results meet or exceed our concurrent 90 nm Cu/FTEOS technology, and support extendibility to 65 nm.

The effect of metal thickness on electromigration-induced extrusion shorts in submicron technology

Various lifetimes and competing failure modes, i.e., extrusion-shorts and void-opens, were found for W via-stud chains with a layered refractory AlCu interconnect. The goal was to specify the reliability scaling trends of multilevel interconnections with respect to interconnect thickness. Interconnection thickness, interconnection current density, and temperature were found to influence W via-stud lifetime and electromigration failure mode. Selectivity between void-open failure and extrusion-short failure was achieved by changing the interconnection thickness or interconnection current density. Contrary to the results obtained with Al, the location of failures along the layered refractory AlCu metal interconnection suggests that the maximum stress gradient generated by electromigration is away from the end of the interconnection. >

Electromigration reliability of AlCu interconnects with W studs

The electromigration behavior of Ti‐AlCu‐Ti metallurgy is presented in this work. For single‐level structures in the absence of tungsten (W) stud interconnections, a greater‐than‐100× lifetime improvement over AlCu is measured. The metal linewidth strongly affects the median time to failure, T50, and standard deviation, sigma (σ), of the lognormal distribution. For two‐level W stud chains, a 50× degradation in lifetime as compared to single‐level structures is measured. The lifetime of these W stud chains depends on the Ti‐AlCu‐Ti current density rather than the stud current density. The ‘‘reservoir effect’’, in which the electromigration lifetime of Ti‐AlCu‐Ti stripes depends strongly on W studs near the electron source end of the stripes, is a direct result of W acting as a diffusion barrier. The lifetime of W stud chains with Ti‐AlCu‐Ti metallurgy is longer for 2.0% copper than for 0.5% copper.

Via Resistance as a Technique to Control the Electromigration of Non-Overlap Via Holes

The via hole in non-overlap vias is larger than the width of the underlaying metal stripe. The upper metal thins down along the slope of the via hole. The extent of thinning depends upon the angle of the via. The reliability of the via can be assured by the control of the slope of the RIE or wet etched via, but this needs SEM analysis which is not possible on a manufacturing line. A series of life test experiments by the step stress method showed that via chains with high resistance resulted in early fails due to electromigration at the thinned down portion of via, and via chains with normal resistance showed good reliability. The results showed that via reliability can be maintained by controlling the via chain resistance below specified limit during the processing of the semiconductor products.