Birendra N. Agarwala

Scaling effect on electromigration in on-chip Cu wiring

Electromigration in on-chip plated Cu damascene interconnections has been investigated for metal line widths from 0.24 /spl mu/m to 1.3 /spl mu/m. Void growth at the cathode end and protrusions at the anode end of the lines have been found to be the main causes of failure. The failure lifetime was found to decrease linearly with decrease in the cross-sectional area of the line. This behavior can be explained by interface diffusion as the dominant path for transport and by the bamboo-like nature of the microstructure. The factor of n for the lifetime dependence on current density for 0.28 /spl mu/m wide lines, /spl tau/=/spl tau//sub 0/j/sup -n/, was found to increase from 1 to 2 as j increased beyond 25 mA//spl mu/m/sup 2/.

Thermal Fatigue Damage in Pb - In Solder Interconnections

Studies were carried out to determine the mechanism of thermal fatigue damage in Pb-In solder interconnections. Based on experimental studies, a model was developed to express the dependence of thermal fatigue life on the stress variables. The morophology of crack nucleation and propagation and the kinetics of crack growth during thermocycling were investigated from fractographic studies.

Width Dependence of Electromigration Life in Al-Cu Al-Cu-Si, and Ag Conductors

The electromigration lifetimes of thin-film Al-Cu, Al-Cu-Si, and Ag conductors were measured as a function of stripe width. Both the median lifetime and the standard deviation of the lognormal failure distribution were observed to depend strongly on the stripe width; this finding indicates that a narrower stripe is less reliable. This width dependence is interpreted in terms of the microstructural characteristics of the films.

Extendibility of PVD barrier/seed for BEOL Cu metallization

The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier and the copper seed layer (Yang, C.-C. et al., MRS Adv. Metallization Conf., p.213, 2004), this new scheme also features a sacrificial process (also called barrier-first process) (Alers, G., IEEE Int. Interconnect Technology Conf., 2003), a via-punch through process (Edelstein, D. et al., IEEE Int. Reliability Physics Symp., p.316, 2004; Kuma, N. et al., MRS Adv. Metallization Conf, p.247, 2004) and a simultaneous preclean with a metal neutral deposition process (Yang et al., US Patent 6,784,105, 2004; Uzoh, C. et al., US Patents 5,930,669, 1999; 5,933,753, 1999; 6,429,519, 2002). Significant metal line and via contact resistance decrease was observed with equal or better reliability. The impact of a sputter etch integration scheme on electrical yield and reliability is also reported. The new sputter scheme decreases contact resistance at the via/interconnect interface and can offset the one resulting from dimension scaling and thus extends PVD metallization usefulness for future technologies.

Electromigration Failure in Au Thin-Film Conductors

Experiments are carried out to understand the electromigration-induced failure mechanism in thin-film Au conductors. The activation energy for the atom transport and the magnitude of the current exponent In the failure equation are obtained. The role of surface coverage on the reliability of AU stripes is studied. The underlying mode of atom transport and the possible sources of flux divergences are discussed in terms of these results.