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Featured researches published by Du B. Nguyen.


international interconnect technology conference | 1999

Scaling effect on electromigration in on-chip Cu wiring

C.-K. Hu; R. Rosenberg; H.S. Rathore; Du B. Nguyen; Birendra N. Agarwala

Electromigration in on-chip plated Cu damascene interconnections has been investigated for metal line widths from 0.24 /spl mu/m to 1.3 /spl mu/m. Void growth at the cathode end and protrusions at the anode end of the lines have been found to be the main causes of failure. The failure lifetime was found to decrease linearly with decrease in the cross-sectional area of the line. This behavior can be explained by interface diffusion as the dominant path for transport and by the bamboo-like nature of the microstructure. The factor of n for the lifetime dependence on current density for 0.28 /spl mu/m wide lines, /spl tau/=/spl tau//sub 0/j/sup -n/, was found to increase from 1 to 2 as j increased beyond 25 mA//spl mu/m/sup 2/.


international interconnect technology conference | 2005

Extendibility of PVD barrier/seed for BEOL Cu metallization

Chih-Chao Yang; Daniel C. Edelstein; Lawrence A. Clevenger; Andy Cowley; J. Gill; Kaushik Chanda; Andrew H. Simon; Timothy J. Dalton; Birendra N. Agarwala; E. Cooney; Du B. Nguyen; Terry A. Spooner; A.K. Stamper

The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier and the copper seed layer (Yang, C.-C. et al., MRS Adv. Metallization Conf., p.213, 2004), this new scheme also features a sacrificial process (also called barrier-first process) (Alers, G., IEEE Int. Interconnect Technology Conf., 2003), a via-punch through process (Edelstein, D. et al., IEEE Int. Reliability Physics Symp., p.316, 2004; Kuma, N. et al., MRS Adv. Metallization Conf, p.247, 2004) and a simultaneous preclean with a metal neutral deposition process (Yang et al., US Patent 6,784,105, 2004; Uzoh, C. et al., US Patents 5,930,669, 1999; 5,933,753, 1999; 6,429,519, 2002). Significant metal line and via contact resistance decrease was observed with equal or better reliability. The impact of a sputter etch integration scheme on electrical yield and reliability is also reported. The new sputter scheme decreases contact resistance at the via/interconnect interface and can offset the one resulting from dimension scaling and thus extends PVD metallization usefulness for future technologies.


Archive | 2005

Structure and method for monitoring stress-induced degradation of conductive interconnects

Kaushik Chanda; Birendra N. Agarwala; Lawrence A. Clevenger; Andrew P. Cowley; Ronald G. Filippi; J. Gill; Tom C. Lee; Baozhen Li; Paul S. McLaughlin; Du B. Nguyen; Hazara S. Rathore; Timothy D. Sullivan; Chih-Chao Yang


Archive | 1997

Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity

Hazara S. Rathore; Hormazdyar M. Dalal; Paul S. McLaughlin; Du B. Nguyen; Richard G. Smith; Alexander J. Swinton; Richard A. Wachnik


Archive | 1998

Method for providing electrically fusible links in copper interconnection

Birendra N. Agarwala; Hormazdyar M. Dalal; Du B. Nguyen; Hazara S. Rathore


Archive | 1996

Method of producing planar metal-to-metal capacitor for use in integrated circuits

Du B. Nguyen; Hazara S. Rathore; George S. Prokop; Richard A. Wachnik; Craig R. Gruszecki


Archive | 1992

Method for producing interlevel stud vias

Du B. Nguyen; Hazara S. Rathore


Archive | 1998

Copper interconnection of sub-quarter micron reducing degree of influence from defect-enhancing electro-migration resistance

Hormazdyar M. Dalal; Du B. Nguyen; S Mclaughlin Paul; Hazara S. Rathore; Richard G. Smith; Alexander J. Swinton; Richard A. Wachnik; アレグザンダー・ジェイ・スウィントン; デュ・ビー・グエン; ハザラ・エス・ラソーア; ポール・エス・マクラフリン; ホルマズドヤール・エム・ダラール; リチャード・エイ・ワクニク; リチャード・ジー・スミス


Archive | 2003

STRUCTURE AND METHOD FOR ELIMINATING TIME DEPENDENT DIELECTRIC BREAKDOWN FAILURE OF LOW-K MATERIAL

Birendra N. Agarwala; Du B. Nguyen; Hazara S. Rathore


Archive | 2005

RELIABILITY AND FUNCTIONALITY IMPROVEMENTS ON COPPER INTERCONNECTS WITH WIDE METAL LINE BELOW THE VIA

Du B. Nguyen; Birendra N. Agarwala; Conrad Albert Barile; Jawahar P. Nayak; Hazara S. Rathore

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