Hector Gomez

A 32-bit RISC-V AXI4-lite bus-based microcontroller with 10-bit SAR ADC

In this paper a complete implementation and design of a fully-synthesized 32-bit microcontroller in a 130nm CMOS technology is presented. This is the first microcontroller featuring the open source RISC-V instruction set all mounted through AXI4-Lite and APB buses for communication process. The microcontroller contains a 10-bit SAR ADC, a 12-bit DAC, an 8-bit GPIO module, a 4kB-RAM, an SPI AXI slave interface for output verification, and an SPI APB slave interface for checking the correct behavioral of the APB bridge. All peripherals are controlled by a RISC-V and an SPI AXI master interface that is used for programming the device and checking the data flowing through all the slaves. A total power density is reported as 167μW/MHz and the area for this RISC-V microcontroller has a reduced footprint of 798μm×484μm.

Mitigating Row Hammer attacks based on dummy cells in DRAM

This paper presents an alternative to prevent data corruption in DRAM memories due to Row Hammer attacks. The proposal is based on the usage of dummy cells connected to each row as attacks indicator. These special cells are characterized for having a higher sensitivity to coupling noise. The strategy was validated by simulations on a 65nm CMOS 64×64 memory array, including process variations for coupling and interconnections. Results keep congruence with a memory dedicated, state-of-art, process of 28nm. The main characteristics of this suggested solution are its low-complexity and low-hardware overhead.

A digital offset correction method for high speed analog front-ends

This paper presents an offset voltage correction technique for high-speed digital interfaces. Contrary to conventional way of measuring offset, the proposed technique is based on the phase measurement of a slicer output avoiding the input connection to a common mode voltage. A fully-digital implementation allows phase measurement maintaining offset accuracy. Proper operation of calibration technique is achieved when the input signal is comparable to the offset and sensitivity of the whole interface. Thus, the proposed method could be used during on-line operation, without breaking the communication link. The circuit has been implemented in a 130nm TSMC standard CMOS process, and simulation results show an offset reduction nearly 90% in the analog front-end with a low area overhead.

A 3.9 compression-ratio Huffman encoding scheme for the large ion collider on 65nm and 130nm CMOS technologies

A Huffman coding scheme with 3.9 compression ratio for the Large Hadron Collider experiment is proposed. A fully-synthesized scheme draws a small footprint layout of 60μm × 60μm in 65nm and 105μm × 105μm in 130nm CMOS process. The maximum operation frequencies are 435MHz for 65nm and 333MHz for 130nm, whereas the power consumption is 1.2mW and 1.9mW respectively. The resulting scheme enables a front-end electronics without any loss of data.

DRAM row-hammer attack reduction using dummy cells

This paper describes a low-cost and low-complexity alternative to reduce the occurrence of Row-Hammer attacks. The detection of an undesired attack is based on the use of an additional memory cell — called dummy cell —, with a larger leakage current and thus a higher sensitivity to crosstalk and coupling noise. This characteristic is achieved due to the use of a wider pass transistor and a smaller storage capacitor. One of the most relevant aspects of this solution is the involved additional low-complexity hardware, occupying less than 0.1% of the whole memory. In addition, the dummy cells can be distributed across the whole memory to hinder hackers identification. Simulations on a 65nm CMOS process were done in order to validate the proposed alternative. Process variations for coupling and interconnections were taken into account in a 64×64 memory array, so that the results keep congruence with a memory dedicate, state-of-art, 28nm process.

A fully-synthesized TRNG with lightweight cellular-automata based post-processing stage in 130nm CMOS

A fully-synthesized true-random number generator (TRNG) using cellular automata as post-processing stage is implemented in an FGPA and in a 130nm CMOS technology. A 3-edge ring oscillator provides the entropy source based on accumulative jitter. The post-processing stage uses a programmable array of cellular automatas and its performance is evaluated for all possible rules that can be constructed. 1.4Mbits are captured using the FPGA implementation and the randomness of data is tested applying NIST tests. One-dimensional cellular automata in a TRNG is reported reducing bias of output data. In addition, the fully-synthesized generator is completely verified for fabrication in 130nm CMOS technology and occupies a final area of 0.0098 mm2 where the post-processing stage uses only 0.0023 mm2.

A fully synthesized key establishment core based on tree parity machines in 65nm CMOS

This paper presents a low-area ASIC implementation of a fully-synthesized symmetric key establishment architecture based on tree parity machines (TPMs) in 130nm and 65nm standard-cell CMOS technologies. The proposed circuit architecture has a serial datapath with re-keying characteristic enabled by a proposed pseudo-random binary sequence (PRBS) generator based on variable-length linear-feedback shift register (LFSR). A circuit technique is proposed that enhances datapath access to add re-keying feature. Fully-synthesized results for 130nm and 65nm show an area consumption of 0.016mm2 and 4800μm2 respectively. Relative area and power consumption are studied by comparing synthesized TPMs with an implementation of a CRC16 error detection code used within security applications. Comparison is made through a proposed figure of merit that include the generated key length in order to show scalability of the architecture with the available technologies.