Hee-seok Kim

Edge-centric modulo scheduling for coarse-grained reconfigurable architectures

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing the potential for high computation throughput, scalability, low cost, and energy efficiency. CGRAs consist of an array of function units and register files often organized as a two dimensional grid. The most difficult challenge in deploying CGRAs is compiler scheduling technology that can efficiently map software implementations of compute intensive loops onto the array. Traditional schedulers focus on the placement of operations in time and space. With CGRAs, the challenge of placement is compounded by the need to explicitly route operands from producers to consumers. To systematically attack this problem, we take an edge-centric approach to modulo scheduling that focuses on the routing problem as its primary objective. With edge-centric modulo scheduling (EMS), placement is a by-product of the routing process, and the schedule is developed by routing each edge in the dataflow graph. Routing cost metrics provide the scheduler with a global perspective to guide selection. Experiments on a wide variety of compute-intensive loops from the multimedia domain show that EMS improves throughput by 25% over traditional iterative modulo scheduling, and achieves 98% of the throughput of simulated annealing techniques at a fraction of the compilation time.

21.4: Development of SLS-Based System on Glass Display

2-inch qVGA (240×320) TFT-LCD with integrated 6-bit source driver is reported. TS-SLS (Two-Shot Sequential Lateral Solidification) technique has been employed to improve the TFT characteristics. Thanks to the superb characteristics of the TS-SLS TFTs, 1:6 de-multiplexing driving scheme has been successfully implemented in the source driver, which resulted very compact circuit area and the highest resolution (200ppi) SOG (System on Glass) display ever reported.

Highly reliable 0.15 μm/14 F2 cell ferroelectric random access memory capacitor using SrRuO3 buffer layer

We investigated a novel technique of modifying the interface between a Pb(ZrxTi1-x)O3 (PZT) thin film and electrodes for high density 64 Mbit ferroelectric random access memory (FRAM) device. Using a SrRuO3 buffer layer, we successfully developed highly reliable 0.15 µm/14 F2 cell FRAM capacitors with 75-nm-thick polycrystalline PZT thin films. The SrRuO3 buffer layer greatly enhanced ferroelectric characteristics due to the decrease in interfacial defect density. In PZT capacitors with a total thickness of 180 nm for whole capacitor stack, a remnant polarization of approximately 42 µC/cm2 was measured with a 1.4 V operation. In addition, an opposite state remnant polarization loss of less than 15% was observed after baking at 150 °C for 100 h. In particular, we found that the SrRuO3 buffer layer also played a key role in inhibiting the diffusion of Pb and O from the PZT thin films.

A highly manufacturable low-k ALD-SiBN process for 60nm NAND flash devices and beyond

For the first time, low-k dielectric ALD-SiBN (atomic layer deposition) is successfully developed and applied on poly-Si/WSix gate as a spacer for reduction of parasitic capacitance between the cells. ALD-SiBN deposition is performed at 630/spl deg/C using dichlorosilane (SiH/sub 2/Cl/sub 2/-DCS), boron-trichloride (BCl/sub 3/) and ammonia (NH/sub 3/) as precursors. Compared with the conventional silicon nitride, ALD-SiBN exhibits similar film properties at lower dielectric constant. ALD-SiBN layer is deposited on poly-Si/WSix stack gate in 90nm NAND flash device. A significant reduction (>15%) of the floating-gate coupling voltage is achieved by employing SiBN compared with SiN spacer. In addition, excellent data retention characteristics (@HTS) is identified by applying low-k dielectric SiBN layer as a spacer on 90nm NAND flash device.

Novel PZT Capacitor Technology for 32Mb and Beyond FRAM Device Using PbTiO 3 Seeding Layer

Effects of the PbTiO 3 (PTO) seeding layer on lowering the PZT crystallization temperature and reducing the capacitor stack height, especially PZT thin film, were systematically investigated. For these purposes, PZT film was modified by using the PTO seeding layer. By using the PTO seeding layer; the crystallization temperature of the PZT film was successfully lowered to 550C. And remanant polarization of PTO-used 100nm thick PZT capacitors measured at 3V was approximately 23 w C/cm 2 , that is 30% higher than that of the PTO-unused PZT capacitors. XRD analysis indicated that the use of the PTO seeding layer remarkably increased the relative intensity of (111) orientation. XRF studies showed that the atomic concentration ratio of Ti-to-Zr was increased by using PTO seeding layers. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Finally, we successfully developed a capacitor stack height of below 400nm, which was composed of Ir/IrO 2 /PZT/Pt/IrO 2 . Furthemore, by lowering the PZT crystallization temperature, small (600 z /contact) and stable contact resistance in a very small size of BC could be obtained.

Investigation on Resistive Memory Switching Mechanism of NiO

ABSTRACT Experimental investigations on the resistive memory switching in sub-micron sized NiO memory cell are presented to elucidate the resistive memory switching mechanism. The voltage or current-biased I-V measurements show that the resistive switching transitions can be regarded as the combination of a voltage-controlled negative differential resistance phenomenon and a current-controlled negative differential resistance phenomenon. Along with experimental observations of multiple resistance states, these indicate that the memory switching in NiO would come from the percolative formation and rupture of filamentary conducting paths. Pulse experiments further suggest that the memory switching would come from local domains inside filaments.