Jin-Gyun Kim

Highly reliable Cu interconnect strategy for 10nm node logic technology and beyond

CVD-Ru represents a critically important class of materials for BEOL interconnects that provides Cu reflow capability. The results reported here include superior gap-fill performance, a solution for plausible integration issues, and robust EM / TDDB properties of CVD-Ru / Cu reflow scheme, by iterative optimization of process parameters, understanding of associated Cu void generation mechanism, and reliability failure analysis, thereby demonstrating SRAM operation at 10 nm node logic device and suggesting its use for future BEOL interconnect scheme.

A highly manufacturable low-k ALD-SiBN process for 60nm NAND flash devices and beyond

For the first time, low-k dielectric ALD-SiBN (atomic layer deposition) is successfully developed and applied on poly-Si/WSix gate as a spacer for reduction of parasitic capacitance between the cells. ALD-SiBN deposition is performed at 630/spl deg/C using dichlorosilane (SiH/sub 2/Cl/sub 2/-DCS), boron-trichloride (BCl/sub 3/) and ammonia (NH/sub 3/) as precursors. Compared with the conventional silicon nitride, ALD-SiBN exhibits similar film properties at lower dielectric constant. ALD-SiBN layer is deposited on poly-Si/WSix stack gate in 90nm NAND flash device. A significant reduction (>15%) of the floating-gate coupling voltage is achieved by employing SiBN compared with SiN spacer. In addition, excellent data retention characteristics (@HTS) is identified by applying low-k dielectric SiBN layer as a spacer on 90nm NAND flash device.

Superior Cu fill with highly reliable Cu/ULK integration for 10nm node and beyond

It is possible to overcome Cu void issues beyond 10nm node device by adapting CVD-Ru liner instead of conventional PVD Ta liner. However, CVD Ru liner integration degrades TDDB performance without optimizing its scheme. In this paper, superior gap-fill performance without TDDB performance degradation will be described in our optimized integration scheme along with a proposal for the mechanism of TDDB degradation in the Ru integration scheme. CVD-Ru liner is the prime candidate for Cu metallization at 10nm node and beyond.

High performance Cu/low-k interconnect strategy beyond 10nm logic technology

CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new processes and materials. This suggests our proposed scheme can be one of promising candidates for 10nm node logic device and beyond.