Ju-Wan Lim

A highly manufacturable low-k ALD-SiBN process for 60nm NAND flash devices and beyond

For the first time, low-k dielectric ALD-SiBN (atomic layer deposition) is successfully developed and applied on poly-Si/WSix gate as a spacer for reduction of parasitic capacitance between the cells. ALD-SiBN deposition is performed at 630/spl deg/C using dichlorosilane (SiH/sub 2/Cl/sub 2/-DCS), boron-trichloride (BCl/sub 3/) and ammonia (NH/sub 3/) as precursors. Compared with the conventional silicon nitride, ALD-SiBN exhibits similar film properties at lower dielectric constant. ALD-SiBN layer is deposited on poly-Si/WSix stack gate in 90nm NAND flash device. A significant reduction (>15%) of the floating-gate coupling voltage is achieved by employing SiBN compared with SiN spacer. In addition, excellent data retention characteristics (@HTS) is identified by applying low-k dielectric SiBN layer as a spacer on 90nm NAND flash device.

Novel Al/sub 2/O/sub 3/ capacitor for high density DRAMs

A poly-Si/Al/sub 2/O/sub 3//poly-Si capacitor is developed for the simple integration of 256 Mb DRAM and beyond. The oxide equivalent thickness (T/sub 0xeq/) of the Al/sub 2/O/sub 3/ capacitor was achieved as small as 28 nm, which is about 1.7 times smaller than that of advanced NO capacitor. Especially, the pre-treatment before the deposition of Al/sub 2/O/sub 3/ film plays a crucial role for stable device performance. Moreover, one of the distinguished characteristics of the Al/sub 2/O/sub 3/ capacitor is that the capacitance was even enhanced by performing the conventional DRAM processes, including the high temperature planarization method known as BPSG flow, without degrading the leakage characteristics.