Hee-Soo Kang

A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory

A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics (IPD), is devised to lesson a high electric field on the FG top edges during program. The cell structure is proved to be promising in sub-20 nm NAND generation in terms of larger program window, better endurance, and more robust data retention, which are obtained by decreasing a leakage current of IPD relating with the electric field on the FG top edges.

Investigation of Tunneling Current in

Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO₂/HfO₂ gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO₂ is not suitable for use in SiO₂/HfO₂ stacks for tunnel barrier engineering applications. The performance of SiO₂/HfO₂ stacks improves with decreasing thickness of the HfO₂ layer. Mild (10%) O₂/N₂ anneals do not significantly affect performance, although annealing above 600°C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO₂/HfO₂ stacks.

\hbox{SiO}_{2}/ \hbox{HfO}_{2}

Abstract We have deposited SiO2 using plasma-enhanced TEOS-based (PE-TEOS) CVD method and USG and PSG using atmosphere-pressure CVD method on Pb(Zr, Ti)O3(PZT) capacitors. The ferroelectric and dielectric properties of the SiO2 covered PZT capacitors were characterized. SIMS (secondary ion mass spectroscopy) was utilized to obtain hydrogen concentration in the deposited ILD and IMD materials. The concentration of hydrogen in the PE-TEOS-derived SiO2 was lower than that in the PSG and the USG. Internal stress was low tensile at room temperature and the behavior of thermal stress hysteresis was nearly similar for all SiO2 materials. Remnant polarization (Pr) of the PE-TEOS covered PZT capacitors was severely degraded as compared to that of as-deposited capacitors. From these results, we have concluded that the degradation of ferroelectric characteristics of PZT capacitors associated with the ILD and IMD processes was closely related to the plasma-induced damage.

Gate Stacks for Flash Memory Applications

The smallest SRAM cell, 0.79 /spl mu/m/sup 2/, was realized by a revolutionary cell layout, fine tuned OPC technique to overcome the 248 nm KrF lithography limitation, instead of using 193 nm ArF lithography. Sub-100 nm CMOS technology was indispensable to achieve the cell size as well as the performance. The high performance transistors were made with 80 nm gate length including 15 /spl Aring/ nitrided gate oxide layer, indium channel and halo implantation processes. The novel cell exhibits excellent neutron SER immunity, compared with ones of the SRAM cell by previous generation technologies.