Suk-kang Sung

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.

SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory

For the multi-gigabit NAND flash memory, SONOS-type FinFET device with p+ gate and high-k blocking dielectric has been integrated both on the cell array and GSL/SSL for the first time. The advantages of the FinFET structure for the NAND flash application have been theoretically and experimentally demonstrated, and the results show that the 85 % improved on-cell current is achievable using FinFET device. The enhanced programming and retention characteristics of FinFET have been also presented, and modeled by the potential changes on fully-depleted body of the sub-40 nm ultra-narrow fin

Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory

Gate-all-around (GAA) MOSFET with single silicon nanowire is fabricated and applied to SONOS memory as a cell transistor for NAND flash string. Driving current over 1 uA, which is sufficient to NAND string, is obtained with single nanowire of ~7 nm width. Using FN tunneling conditions, VTH window of 4.5 V and fast program/erase (P/E) speed of ~10 us are obtained, respectively. The smaller nanowire width is, the faster program speed and the larger VTH shift are achieved. P/E operations in NAND string with GAA SONOS nanowire are demonstrated for the first time.

Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

This paper presents the trap layer engineered body-tied FinFET device for MLC NAND flash application. The device design parameters for high density NAND flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure

A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um2 (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning Technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.

Hot carrier generation and reliability of BT(body-tied)-Fin type SRAM cell transistors (W/sub fin/=20/spl sim/70 nm)

In this paper, we fabricated a BT-FinFET SRAM device with the smallest cell size of 0.46 /spl mu/m/sup 2/. And a hot carrier generation mechanism in the FinFET is thoroughly evaluated by measuring the I/sub sub/ of the BT-FinFET for various Si fin widths (20/spl sim/70 nm). For the first time, we revealed the mechanism of improved hot carrier immunity of sub 50 nm fin type MOSFETs.

Retention Reliability of FinFET SONOS Device

This paper presents the retention reliability of the FinFET SONOS flash memory. By understanding the charge loss mechanisms of the SONOS structure, a new approach for the prediction of long term retention lifetime have been proposed. The comparison between the thermal-accelerated and field-accelerated lifetime has been demonstrated

Hf-silicate inter-poly dielectric technology for sub 70nm body tied FinFET flash memory

We report for the first time on 256Mb NOR-type body tied FinFET flash memory using Hf silicate IPD (inter poly dielectric) and compare with FinFET flash memory using traditional ONO IPD. An enlarged coupling ratio through Hf silicate IPD enhanced a CHEI (channel hot electron injection) programming speed and made the operation voltage down. And we could obtain a higher erasing speed resulted from HHI (hot hole injection) erase than that of F-N tunneling without degrading endurance characteristics.

Investigation on the Retention Reliability of Scaled

We investigate the retention reliability of a 51-nm-node 16-GB nand Flash cell transistor comprising SiO₂/Al_xO_y/SiO₂ inter-poly dielectric (OAO IPD). Despite the fact that OAO IPD retains low trapping rate being beneficial to retention reliability, the trap sites are located on shallow energy level, yielding a large amount of trap-assisted tunneling current at high temperature. Therefore, experimental results show two incompatible data retention characteristics of OAO IPD, namely, 33% worse <i>V</i> _TH shift at 200°C 2-h bake and 53% improved <i>V</i> _TH shift after one week at 25°C, when compared to the case of ONO IPD.

\hbox{SiO}_{2}/\hbox{Al}_{x}\hbox{O}_{y}/\hbox{SiO}_{2}

Thanks to the combination of damascene gate and outer poly-Si sidewall spacer process, we have successfully fabricated twin silicon–oxide–nitride–oxide–silicon (SONOS) memory (TSM) transistors with 20-nm twin nitride storage nodes under an 80-nm gate. In terms of device manufacturability, the damascene gate process makes it possible to realize physically separated structure and the outer poly-Si sidewall spacer scheme contributes to realization of 20-nm long nitride storage node. Compared with conventional SONOS transistor, the fabricated TSM transistor maintains its threshold voltage margin between the forward and reverse reads down to 80-nm long gate. The TSM transistor also shows stable and reliable characteristics: up to 105 program/erase cycles endurance and fairly good bake retention at 150°C.