Dong-uk Choi

Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application

We have successfully fabricated sub 30nm N+ poly and TiN gate MBCFET (multi-bridge-channel field effect transistor) both on SOI wafers and bulk-Si wafers. Using TiN metal gate and 20nm multi bridge channels, we achieved the drive current of 2.3mA//spl mu/m that is the largest drive current ever reported for pMOSFETs with excellent subthreshold swing of 75mV/dec, and drain induce barrier lowering (DIBL) of 36mV/V. Large I/sub on//I/sub off/ ratio and excellent threshold voltage (V/sub t/) distribution were obtained using TiN metal gate to eliminate channel ion implantation minimizing the mobility degradation and dopant fluctuation.

A high performance 16M DRAM on a thin film SOI

A fully working 16M DRAM on a Thin Film Silicon On Insulator (TFSOI) is made with 0.5 /spl mu/m CMOS technology. This is, to the best of our knowledge, the highest density SOI DRAM ever achieved. LOCOS isolation and Local Implantation post Field oxidation (LIF) are introduced to suppress the edge transistor effect in NMOS. A reduced n/sup +//p/sup +/ dose in S/D implantation is the key process for a high density TFSOI-DRAM to suppress the defect generation during process while drain-source breakdown voltage (BVds) being increased. The shmoo plot of supply voltage vs. TRAC at 25/spl deg/C for a TFSOI-DRAM is demonstrated. RAS access time, TRAC, is 50 ns at 3.0 V Vcc which is faster by 20% than that of the equivalent bulk-Si device.

SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory

For the multi-gigabit NAND flash memory, SONOS-type FinFET device with p+ gate and high-k blocking dielectric has been integrated both on the cell array and GSL/SSL for the first time. The advantages of the FinFET structure for the NAND flash application have been theoretically and experimentally demonstrated, and the results show that the 85 % improved on-cell current is achievable using FinFET device. The enhanced programming and retention characteristics of FinFET have been also presented, and modeled by the potential changes on fully-depleted body of the sub-40 nm ultra-narrow fin

Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

This paper presents the trap layer engineered body-tied FinFET device for MLC NAND flash application. The device design parameters for high density NAND flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure

Data retention times in SOI-DRAMs

Refresh characteristics in SOI-DRAMs are discussed. Compared with bulk-Si DRAMs, excellent static refresh characteristics in SOI-DRAMs were obtained, owing to the inherently reduced junction area. Inferior dynamic refresh characteristics in SOI-DRAMs were measured due to the floating body, but this can be overcome by a pipe channel doping structure.

Improved performance of multi-giga bit NAND flash using channel orientation

In this paper, we report the enhanced performance of multi-giga bit NAND flash memory through the combined effects of uniaxial compressive stress and <100>-oriented channel engineering. Using this method, cell current increased more than 29% owing to the mobility enhancement of the narrow width (60 nm) flash cell. Reduced interface trap with the active edge of <100> channel resulted in the endurance characteristic improvement ~5%.

Hot carrier issues in thin body double-gate MOSFET

In this paper, the hot carrier reliability of double gate (DG) MOSFETs is evaluated by simulations. The effect of floating body and volume inversion on hot carrier injection in DG is studied. It proves that thin body DG has good immunity to hot carrier injection into the gate electrodes. And for the application of DG in nonvolatile memory, an effective method is suggested to control the hot carrier injection in DG.