Kwang Pyuk Suh

Highly manufacturable SONOS non-volatile memory for the embedded SoC solution

A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 /spl mu/m standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the complete erase, low program current, and high on cell current from the low threshold voltage. The entire embedded memory solution has been realized with 0.276 /spl mu/m/sup 2/ Local SONOS NVM cell, which has 20 /spl mu/s program and 2 ms erase speed under 5.5 V bias condition, and good reliability without the special algorithms and cell array modifications.

Large scale integration and reliability consideration of triple gate transistors

Large scale integration and reliability of triple gate FETs (TG-FETs) are investigated. The SRAM chip composed of TG-FETs demonstrated 20Mbits of working cells, and 45/spl deg/ rotated TG-FET is found to be superior from reliability perspective. Future TG-FET design is proposed, utilizing technologies including alternating phase shift mask lithography, local-interconnects and metal gate/undoped channel.

A 0.25-/spl mu/m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

A 0.25-/spl mu/m, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm/sup 2/ silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test.

Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications

Manufacturable embedded CMOS 6T-SRAM with the HfO/sub 2/-Al/sub 2/O/sub 3/ dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11/spl mu/m NFET and PFET devices with thin high-k gate dielectric have 470 and 150/spl mu/A//spl mu/m at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14/spl mu/m/sup 2/ 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.

50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

An alternative interpretation of hot electron interface degradation in NMOSFETs: isotope results irreconcilable with major defect generation by holes?

The giant deuterium isotope effect found previously for NMOS hot electron degradation is applied to study defect generation at the Si-SiO/sub 2/ interface. The data suggest that interface defects related to hydrogen depassivation may be generated directly by channel hot electrons bombarding the interface without the necessity of injection into the oxide. This is in contrast to the standard teaching that energetic holes, created by impact ionization, and injected into the oxide are the main cause for hydrogen-related defect generation at the Si-SiO/sub 2/ interfaces.

Thermally robust Ta-doped Ni SALICIDE process promising for sub-50 nm CMOSFETs

For sub-50 nm device application, Self-Aligned siLICIDE (SALICIDE) process by NiTa alloy has been developed for the first time. Use of NiTa-alloy makes nickel silicide on 50 nm gate thermally-robust up to 600/spl deg/C during device fabrication. NiTa SALICIDE process can also achieve excellent value and distribution of sheet resistance on 30 nm gate as well as low junction leakage current compared to Co SALICIDE. Furthermore, the drive current of PMOS is greatly increased. As a result, high-performance 90 nm MOSFETs is successfully integrated with NiTa SALICIDE process.

Double raised source/drain transistor with 50 nm gate length on 17 nm UTF-SOI for 1.1 /spl mu/m/sup 2/ embedded SRAM technology

Double raised source/drain (DR) ultra thin film (UTF) SOI CMOSFETs were experimented for the first time. Double Si selective epitaxial growth (SEG) process before source/drain extension and deep source/drain implant is greatly recommended for excellent device performance with a reduced series resistance. Fully depleted (FD) SOI devices with 50 nm gate length for embedded SRAM technology were investigated for different SOI film thickness. Transistor performances of 700 /spl mu/A//spl mu/m and 355 /spl mu/A//spl mu/m at 1.0 V operation and Ioff = 90 nA//spl mu/m was obtained for NMOS and PMOS devices, respectively. Drain induced barrier lowering (DIBL) was improved as the SOI film thickness was scaled down to 17 nm from 50 nm. The static noise margin (SNM) for a 1.1 /spl mu/m/sup 2/ SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.

Advanced i-PVD barrier metal deposition technology for 90 nm Cu interconnects

An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.

Re-defining reliability assessment per new intra-via Cu leakage degradation

By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.