T. Park

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I/sub SUB//I/sub D/ than planar type DRAM cell transistors.

An optimized densification of the filled oxide for quarter micron shallow trench isolation (STI)

Densification methods using H/sub 2/O and N/sub 2/ ambient annealing of the filled CVD oxide for quarter micron STI are compared. Although the H/sub 2/O ambient oxidation is more effective in terms of the resistance against the HF etching, volume expansion by the trench sidewall oxidation generates a large amount of stress in the narrow isolation region. However, an N/sub 2/ gas ambient annealing at high temperature shows a low stress and a low HF etch rate which enable us to fabricate the stable quarter micron STI.

Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides

We have found that the defect generation which is induced by the mechanical stress during the densification, depends on the ratio of the trench filling material composed of the TEOS-O/sub 3/ based CVD oxide with tensile stress and the plasma enhanced CVD oxide with compressive stress. The lower as-deposited stress is, the lower the maximum stress during the densification is. This stress level is proportional to the defect density which is generated in fabricating MOSFETs with Shallow Trench Isolation (STI). In order to achieve devices without a defect, it is important to minimize as-deposited stress level by optimizing the ratio of the trench filling CVD oxides.

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

Tungsten silicide/titanium nitride compound gate for submicron CMOSFET

Experimental results are presented for a WSi2/TiN compound-gate MOSFET with a near-midgap work function ranging from 4.63 to 4.75 eV and low resistivity. Sheet resistances of the compound gate and the conventional n+ gate with and without the interconnection layer are studied, and it is shown that the compound gate materials are an adequate interconnection layer. When positive bias is applied to the gate, the tunneling current of a compound-gate MOS is similar to that of an n+-poly-gate MOS with and without interconnection layer. This is because electrons are tunneling through the oxide from the silicon substrate to the gate, so that the barrier height is defined dominantly by the oxide barrier from the silicon substrate

Modeling of cumulative thermo-mechanical stress (CTMS) produced by the shallow trench isolation process for 1 Gb DRAM and beyond

The defects induced by the thermo-mechanical stress in the device fabrication process are correlated with device characteristics of 1 Gb DRAM. To identify the defect formation in the thermal process, we modeled the cumulative thermo-mechanical stress (CTMS) throughout the shallow trench isolation (STI) integrated DRAM process, and performed computer simulation using ABAQUS. The defect-free stress level was extracted from the relationship between the cumulative shear stress and electrical device characteristics, and then applied to optimizing thermal annealing process to obtain the defect-free process condition for the fabrication of 1 Gb DRAM and beyond.

PMOS body-tied FinFET (Omega MOSFET) characteristics

In this paper, we introduce PMOS body-tied FinFet characteristics. For this work, the 0.1/spl mu/m design ruled SRAM technology was used. I/sub D/-V/sub DS/ characteristics show that /spl Omega/ MOSFET apparently has lower DIBL characteristics than conventional PMOS transistor. On current of the /spl Omega/ MOSFET is higher than that of conventional device and can be improved by optimising unit processes.

50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

Correlation between gate oxide reliability and the profile of the trench top corner in Shallow Trench Isolation (STI)

In order to develop a Shallow Trench Isolation (STI) which does not have trench corner induced degradation of the gate oxide, its integrities were evaluated with rounded, non-rounded top corner, and an addition of CVD SiO/sub 2/ spacer. In the experiment, we found that the rounded and SiO/sub 2/ spacered STI showed the best result meaning no harmful influence of the corner to the gate oxide integrity. Also, etch-back processes of the filled CVD SiO/sub 2/ were modified to eliminate the degradation of the gate oxide by a stress concentration at top corner kinks.

Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)

Electrostatic channel extension (ESCE) MOSFET, a transistor with static inversion layer formed by interface fixed charge is fabricated in planar bulk structure down to 20 nm gate-length. The 24 nm gate-length ESCE transistor with current 80 nm gate-length SRAM technology shows the excellent drive currents of 1.0 mA/mum with IOFF of 93 nA/mum at VDS = 1 V. Moreover, the ESCE transistor with the gate oxide thickness of 10 Aring shows effectively suppressed gate-oxide leakage, very low GIDL, high breakdown voltage (> 6 V), immunity from CD variance, and robust reliability. The ESCE scheme is very promising to overcome the scale-down limit of planar transistor beyond 20 nm with ultra-low cost