Helena Kruus

A hybrid BIST architecture and its optimization for SoC testing

This paper presents a hybrid BIST architecture and methods for optimizing it to test system-on-chip in a cost effective way. The proposed self-test architecture can be implemented either only in software or by using some test related hardware. In our approach we combine pseudorandom test patterns with stored deterministic test patterns to perform core test with minimum time and memory, without losing test quality. We propose two algorithms to calculate the cost of the rest process. To speed up the optimization procedure, a Tabu search based method is employed for finding the global cost minimum. Experimental results have demonstrated the feasibility and efficiency of the approach and the significant decreases in overall test cost.

Hybrid BIST Optimization Using Reseeding and Test Set Compaction

Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and to reduce test time. We will propose a novel method for hybrid BIST optimization, based on reseeding and test set compaction. The objective is to minimize the test time at given test memory constraints, without losing test quality. We will compare the proposed method with hybrid BIST methods developed earlier and analyze its suitability for testing core-based systems.

Hybrid BIST optimization using reseeding and test set compaction

Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and to reduce test time. We will propose a novel method for hybrid BIST optimization, based on reseeding and test set compaction. The objective is to minimize the test time at given test memory constraints, without losing test quality. We will compare the proposed method with hybrid BIST methods developed earlier and analyze its suitability for testing core-based systems.

Optimization of the Store-and-Generate Based Built-in Self-Test

Classical built-in self-test (BIST) architectures are usually relying on linear feedback shift registers (LFSR) for test set generation and test response compaction. This paper is based on extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with precomputed deterministic test patterns to increase the fault coverage and reduce test time. We will propose a method, based on store-and-generate approach, to find the optimal balance between pseudorandom and stored deterministic test patterns. The objective is to minimize the test time at given memory constraints, without losing test quality. We propose an iterative search method and the experimental results on benchmark circuits have proved the efficiency of the proposed approach for hybrid BIST optimization

Teaching modeling in SysML/UML and problems encountered

Over the past years information and communication technology has evolved with an increasing speed - new technologies, systems, applications are released faster than ever. However, to be successful in their lifecycle, systems need to be carefully modelled beforehand to mitigate several risks a new product or application launch might hinder, biggest of them of course the risk of failure. This sets strong prerequisites and expectations towards young engineers, and on teaching future system engineers. In this paper we address the issues of teaching systems modelling in SysML and UML for students of Computer and Systems Engineering curriculum together with problems encountered.

SysML in systems engineering course

Systems engineering is defined as a discipline that guides the engineering of complex systems. It is essential to have a special course covering the issues and aspects of systems engineering in engineering curricula in order to provide the students with multidisciplinary knowledge and experience, and to ensure quality of learning outcomes. Students should have extensive knowledge not only about the components of system but also the ability to see a system as a whole, its lifecycle, requirements and the role of these requirements, using specifications throughout design process, system testing, maintenance and management. We have developed such an introductory course for the first year students of Computer and Systems Engineering Masters programme, covering these essential topics of systems engineering. As a latest addition to the course, introduction to SysML, its practical use in modeling of different subsystems and the system as a whole, and an overview of available tools has been included to the course to provide modern approach to practical hands-on exercises.

A benchmark suite for evaluating the efficiency of test tools

We propose a benchmark suite for systematic evaluation of efficiency of new CAD and test algorithms. The suite consists of a set of high performance signal processors. Differently from all other existing benchmark suites, all the member processors of this family perform the same function, but are implemented in different ways, differing mainly in sharing of computing resources. The circuits are characterized by different structural complexities measured in the number of reconvergent fan-outs. The latter feature has the main impact to the testability of circuits, influencing directly on the efficiency of test tools and on the quality of the given test set. The main advantage of the benchmark suite, compared to the existing ones, relies in the possibility to create systematic dependencies of the efficiency of test algorithms or test quality as a function of the structural complexity of circuits.

Laboratory framework TEAM for investigating the dependability issues of microprocessor systems

We propose a laboratory research and student training oriented framework consisting of Test Evaluation Automated Means (TEAM) as a set of tools for evaluating the quality of test programs for microprocessors and systems. TEAM enables students to learn and analyze the dependability issues of microprocessor systems, to create their own designs and develop test programs, to analyze the quality of testing, and to make decisions about improving the testability of systems. The tool set in TEAM is mostly open and consists of the assembly level test converter, register transfer level test program simulator, global test converter into local test sequences for modules of the system, and gate-level fault simulator. The general ideas of hands-on laboratory training supported by TEAM are outlined. The research tasks of test program generation can be set up in a way that enables a competition between students, and as a consequence, motivates them to better understand the problems of testing of complex systems and their dependability.

Hardware close programming for freshmen

For the future engineers, it is important during their studies to connect the acquired knowledge learned with the real life. It is also important to understand the problems and have the ability to apply their fresh knowledge know-how in solving different tasks. This paper concentrates on providing students with the possibility to apply their software-oriented programming skills to hardware implementations during the first year of their studies. Two different platforms are described - based on embedded microcontroller and FPGA solutions, providing various hands-on exercises for both individual assignments and teamwork. Both proposed task groups are accompanied with thorough documentation and web-based study material. Through solving the provided tasks, the students are able to get more clear comprehension of applying their skills to real-life problem solving.

Involving students in teaching process — Encouraging student-generated content in ICT studies

This paper deals with new paradigms rising in contemporary teaching, where classical “teacher-to-student” approach is shifting to more flexible and diverse ways of teaching and learning. We describe our experience at the Department of Computer Engineering of Tallinn University of Technology in involving engineering students into the process of creating learning content on various ICT subjects.