Hemanshu D. Bhatt

Self-aligned cell integration scheme

In situ measurement

Nano structure electrode design

SPACER-LESS TRANSISTOR INTEGRATION SCHEME FOR HIGH-K GATE DIELECTRICS AND SMALL GATE-TO-GATE SPACES APPLICABLE TO SI, SIGE AND STRAINED SILICON SCHEMES

Integrated circuit with inductor having horizontal magnetic flux lines

Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines

Local interconnect manufacturing process

Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing

Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing

Shallow trench isolation depth extension using oxygen implantation