Byung-Sung Kwak

Integrated barrier and seed layer for copper interconnect technology

Self-aligned cell integration scheme

Method of fabricating an alloy cap layer over CU wires to improve electromigration performance of CU interconnects

Method for fabricating planar semiconductor wafers

Forming copper interconnects with Sn coatings

Method and apparatus for diverting void diffusion in integrated circuit conductors

Method for improved local planarity control during electropolishing

PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER

Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design

Contact ring design for reducing bubble and electrolyte effects during electrochemical plating in manufacturing