Jayanthi Pallinti

Electrical characterization of the copper CMP process and derivation of metal layout rules

Design rules were developed for the layout of copper Damascene interconnect layers to minimize the within-die resistance variation. The impact of various layout configurations on the metal sheet resistance was characterized using two different test vehicles. An increase in resistance was observed on wide lines and high pattern densities due to dishing and dielectric erosion, respectively. In addition to the above, narrow lines were severely impacted by the presence of wide adjacent features in close proximity. The pattern interaction distance for copper chemical-mechanical planarization (CMP) was calculated by analyzing the resistance variation at the edge of a density or width transition. In this work, the interaction distance was found to be on the order of 25 /spl mu/m (as opposed to a few millimeters for oxide CMP). From these results, a window of about 50 to 60 /spl mu/m was found to be necessary to obtain the effective pattern density for copper CMP. The resistance of the upper metal level was a strong function of the underlying layer density. Hence, multilevel pattern dependencies have to be considered when modeling and predicting the line resistance on a real design. However, unlike oxide polish, pattern density alone is insufficient to predict the final copper thickness. Width-dependent spacing rules are necessary to prevent clustering of features (narrow lines very close to wide buses) and avoid regions of very low density.

Design rule methodology to improve the manufacturability of the copper CMP process

A systematic approach to generate design rules and layout guidelines for damascene metal layers that enhance the robustness and manufacturability of designs is presented. The intra-die sheet resistance variation due to line width and pattern density effects is characterized for single and multi-level interconnects and the feature interaction distance is determined to be about 30 /spl mu/m. It is shown that the best way to minimize the sheet resistance spread is by implementing rules for the minimum and maximum space between any two features as a function of their widths.

An overview of stress free polishing of Cu with ultra low-k(k<2.0) films

An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed.