Hemant Pardeshi

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0:83In0:17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (Vt/, Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

Comparative assessment of III-V heterostructure and silicon underlap double gate MOSFETs

Comparative assessment of III–V heterostructure and silicon underlap DG-MOSFETs, is done using 2D Sentaurus TCAD simulation. III–V heterostructure device has narrow-band In0.53Ga0.47As and wide-band InP layers for body, and high-K gate dielectric. Density gradient model is used for simulation and interface traps are considered. Benchmarking of simulation results show that III–V device provides higher on current, lesser delay, lower energy-delay product and lower DIBL than silicon device. However III–V device has higher SS and lower Ion/Ioff than silicon device. The results indicate that there is a need to optimize the Ion/Ioff, SS and DIBL values for specific circuits.

Flicker and thermal noise in an n-channel underlap DG FinFET in a weak inversion region

We propose an analytical model for drain current and inversion charge in the subthreshold region for an underlap DG FinFET by using the minimum channel potential method, i.e., the virtual source. The flicker and thermal noise spectral density models are also developed using these charge and current models expression. The model is validated with already published experimental results of flicker noise for DG FinFETs. For an ultrathin body, the degradation of effective mobility and variation of the scattering parameter are considered. The effect of device parameters like gate length Lg and underlap length Lun on both flicker and thermal noise spectral densities are also analyzed. Increasing Lg and Lun, increases the effective gate length, which reduces drain current, resulting in decreased flicker and thermal noise density. A decrease of flicker noise is observed for an increase of frequency, which indicates that the device can be used for wide range of frequency applications.

A 2DEG charge density based drain current model for various Al and In molefraction mobility dependent nano-scale AlInGaN/AlN/GaN HEMT devices

We present a two-dimensional electron gas (2DEG) charge-control mobility variation based drain current model for sheet carrier density in the channel. The model was developed for the AlInGaN/AlN/GaN high-electron-mobility transistor. The sheet carrier density model used here accounts for the independence between the Fermi levels Ef and ns along with mobility for various Al and In molefractions. This physics based ns model fully depends upon the variation of Ef, u0, the first subband E0, the second subband E1, and ns. We present a physics based analytical drain current model using ns with the minimum set of parameters. The analytical results obtained are compared with the experimental results for four samples with various molefraction and barrier thickness. A good agreement between the results is obtained, thus validating the model.

Effect of Barrier layer thickness on device performance of AlInN/GaN Underlap DG MOSFET

We analyze the influence of Al0.83In0.17N barrier layer thickness (TB) on device performance of 18nm gate length ultra thin body AlInN/GaN heterostructure underlap DG MOSFET, using 2D Sentaurus TCAD simulation. The device is designed according to the ITRS specifications and simulation is done using the hydrodynamic model. The simulation is validated with previously published experimental results. Very high drain current density (~8.8 mA/μm) is achieved, due to high values of two-dimensional electron gas (2DEG) density and velocity. Simulation of major device performance parameters such as DIBL, SS, delay, threshold voltage (Vt), ON current, energy delay product and total gate capacitance Cgg have been done for TB ranging from 0nm to 4nm. As TB is increased the drain current increases and delay decreases, but at the expense of loss of electrostatic control leading to increased short channel effect i.e. higher DIBL and SS. Also, negative shift in threshold voltage is observed for rising TB. Decrease in Cgg is observed as TB increases, due to increase in separation between the gate and channel, leading to reduced gate control. There is tradeoff between achieved drain current and electrostatic control for varying TB Thus, the selection of appropriate TB is of vital significance as it determines the device performance.

Effect of Barrier Thickness on Linearity of Underlap AlInN/GaN DG-MOSHEMTs

In this proposed work, an extensive study on the linearity performance of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) has been analyzed using 2D Sentaurus TCAD simulation. Specifically a brief comparison is made on the linearity and intermodulation distortion characteristics of the proposed device due to variation of barrier layer thickness from 2 nm to 6 nm. Various parameters such as transconductance (gm), second-order transconductance (gm2), third-order transconductance (gm3), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3) and third-order intermodulation distortion (IMD3) of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) are discussed. The simulated results obtained confirms that by careful optimization of barrier layer thickness linearity characteristics of this proposed device can be improved, which can be suitable for analog and circuit applications.

Effect of AlN Spacer Layer Thickness on Device Performance of AIInN/AlN/GaN MOSHEMT

In the present work, we have analyzed the influence of AlN spacer layer thickness (ts) on the device performances of a 120-nm gate length AlInN/AlN/GaN MOS-HEMT device, using 2D Sentaurus TCAD simulation. A hydrodynamic model with due consideration of interface traps is used for the simulations. Due to the high value of the two-dimensional electron gas (2DEG) density and mobility in the AlInN/AlN/GaN MOS-HEMT device, a very high drain current (0.004 A/μm) density is achieved. Simulation of major device performance parameters such as Tran conductance (gm), cutoff frequency (ft) and total gate capacitance (Cgg) have been done for ts ranging from 0.5 nm to 2 nm. We have also optimized the spacer layer thickness for obtaining the maximum device performance.

Analysis of flicker and thermal noise in p-channel Underlap DG FinFET

Abstract In this paper, we analyze the flicker and thermal noise model for underlap p-channel DG FinFET in weak inversion region. During the analysis of current and charge model, minimum channel potential i.e. virtual source is considered. Initially, the drain current for both long and short channel of DG FinFET are evaluated and found to be well interpreted with experimental results. Further, the flicker and thermal noise spectral density are derived. The flicker noise power spectral density is compared with published experimental results, which shows a good agreement between proposed model and experimental result. During calculation we have considered variation of scattering parameter and furthermore, the degradation of effective mobility is taken into account for ultrathin body. The variation of structural parameters such as gate length (Lg), body thickness (tSi) and underlap length (Lun) are also considered. The degradation of gate noise voltage with frequency, underlap length and gate length signify that p-channel DG FinFET device can be a promising candidate for analog and RF applications.