Sarosij Adak

Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs

Abstract In this paper, the graded channel gate stack (GCGS) DG MOSFET structure is studied in view of increasing device performance and immunity to short channel effects. The device has the advantage of improved gate oxide reliability, suppressed parasitic bipolar effect, lower DIBL and higher cut-off frequency. Therefore, the device must be investigated with respect to the variation of different structure dependent parameters before fabrication to have better reliability and constancy. In this work we have studied the device with respect to variation in high K oxide thickness (t oxh ) and channel length (L g ) to have better understanding on variation of different analog/RF performance parameters. The results validate that variations in t oxh of the device significantly alters device performance parameters and must be pre accounted for realizing reliable analog/RF system on chip circuits.

Influence of Channel Length and High-K Oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate Stack DG-MOSFETs

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), Ion/Ioff, Vth roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.

Effect of Barrier Thickness on Linearity of Underlap AlInN/GaN DG-MOSHEMTs

In this proposed work, an extensive study on the linearity performance of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) has been analyzed using 2D Sentaurus TCAD simulation. Specifically a brief comparison is made on the linearity and intermodulation distortion characteristics of the proposed device due to variation of barrier layer thickness from 2 nm to 6 nm. Various parameters such as transconductance (gm), second-order transconductance (gm2), third-order transconductance (gm3), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3) and third-order intermodulation distortion (IMD3) of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) are discussed. The simulated results obtained confirms that by careful optimization of barrier layer thickness linearity characteristics of this proposed device can be improved, which can be suitable for analog and circuit applications.

Effect of AlN Spacer Layer Thickness on Device Performance of AIInN/AlN/GaN MOSHEMT

In the present work, we have analyzed the influence of AlN spacer layer thickness (ts) on the device performances of a 120-nm gate length AlInN/AlN/GaN MOS-HEMT device, using 2D Sentaurus TCAD simulation. A hydrodynamic model with due consideration of interface traps is used for the simulations. Due to the high value of the two-dimensional electron gas (2DEG) density and mobility in the AlInN/AlN/GaN MOS-HEMT device, a very high drain current (0.004 A/μm) density is achieved. Simulation of major device performance parameters such as Tran conductance (gm), cutoff frequency (ft) and total gate capacitance (Cgg) have been done for ts ranging from 0.5 nm to 2 nm. We have also optimized the spacer layer thickness for obtaining the maximum device performance.