Sudhansu Kumar Pati

Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs

Abstract The underlap double gate MOSFET (UDG-MOSFET) has been well established as a potential candidate for the RF applications. However, before implementation the various process related variations are required to be addressed for the better dependability. In this paper, the effect of process dependent parameter variations on the RF performance of the UDG-MOSFET is analyzed. The process dependent parameters considered are the oxide and the body thicknesses. The RF performance of UDG-MOSFET is analyzed as a function of RF figure of merits (FOMs), intrinsic capacitance (Cgs, Cgd), intrinsic resistance (Rgs, Rgd), transport delay (τm), inductance (Lsd) and analog FOMs transconductance (gm), transconductance generation factor (gm/Id), output resistance (Ro) and intrinsic gain (gmRo). The analysis is performed using the non-quasi static (NQS) small signal model of the UDG-MOSFET.

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0:83In0:17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (Vt/, Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

Comparative assessment of III-V heterostructure and silicon underlap double gate MOSFETs

Comparative assessment of III–V heterostructure and silicon underlap DG-MOSFETs, is done using 2D Sentaurus TCAD simulation. III–V heterostructure device has narrow-band In0.53Ga0.47As and wide-band InP layers for body, and high-K gate dielectric. Density gradient model is used for simulation and interface traps are considered. Benchmarking of simulation results show that III–V device provides higher on current, lesser delay, lower energy-delay product and lower DIBL than silicon device. However III–V device has higher SS and lower Ion/Ioff than silicon device. The results indicate that there is a need to optimize the Ion/Ioff, SS and DIBL values for specific circuits.

Flicker and thermal noise in an n-channel underlap DG FinFET in a weak inversion region

We propose an analytical model for drain current and inversion charge in the subthreshold region for an underlap DG FinFET by using the minimum channel potential method, i.e., the virtual source. The flicker and thermal noise spectral density models are also developed using these charge and current models expression. The model is validated with already published experimental results of flicker noise for DG FinFETs. For an ultrathin body, the degradation of effective mobility and variation of the scattering parameter are considered. The effect of device parameters like gate length Lg and underlap length Lun on both flicker and thermal noise spectral densities are also analyzed. Increasing Lg and Lun, increases the effective gate length, which reduces drain current, resulting in decreased flicker and thermal noise density. A decrease of flicker noise is observed for an increase of frequency, which indicates that the device can be used for wide range of frequency applications.

A 2DEG charge density based drain current model for various Al and In molefraction mobility dependent nano-scale AlInGaN/AlN/GaN HEMT devices

We present a two-dimensional electron gas (2DEG) charge-control mobility variation based drain current model for sheet carrier density in the channel. The model was developed for the AlInGaN/AlN/GaN high-electron-mobility transistor. The sheet carrier density model used here accounts for the independence between the Fermi levels Ef and ns along with mobility for various Al and In molefractions. This physics based ns model fully depends upon the variation of Ef, u0, the first subband E0, the second subband E1, and ns. We present a physics based analytical drain current model using ns with the minimum set of parameters. The analytical results obtained are compared with the experimental results for four samples with various molefraction and barrier thickness. A good agreement between the results is obtained, thus validating the model.

A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

In analog circuit design an important parameter, from the perspective of superior device performance, is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addition to that it provides, at the discretion of analog circuit designer, an additional degree of freedom, by providing independent bias control for the front and the back gates. Here a non-quasi-static (NQS) small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD simulations. The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance, Cgd1 and Cgd2, the intrinsic front and back distributed channel resistance, Rgd1 and Rgd2 respectively, the transport delay, τm, and the inductance, Lsd. The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data, for symmetric DG MOSFET devices, from the available literature. The device simulation is performed with respect to frequency up to 100 GHz.