Henning Gundersen

Ultra-low-voltage floating-gate transconductance amplifiers

Ultra-low-voltage (ULV) floating-gate differential amplifiers are presented. In this paper, we present several different approaches to CMOS ULV amplifier design. Sinh-shaped and tanh-shaped transconductance amplifiers are described. Measured results are provided.

A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices

This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged Semi- Floating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.

Max and min functions using Multiple-Valued Recharged Semi-Floating Gate circuits

In this paper we present a new proposal for implementing a voltage-mode Multiple-Valued (MV) maximum or minimum function. The circuit has been implemented using Recharged Semi Floating-Gate (SFG) transistors. The benefit with this design is, the proposed circuits can easily be fabricated using a conventional CMOS process. The circuit is suitable for a low power design, V/sub dd/<2 volt. It has high noise margin and good linearity. The simulation results for the proposed circuit are evaluated using AMS 0.35 /spl mu/m CMOS device parameters.

Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices

This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative and positive operands, by using the same adder blocks. The circuit operates at a clock frequency of 1 Ghz. The supply voltage 1.0 Volt.

Ultra Low-Voltage Floating-Gate (FGUVMOS) Amplifiers

This paper presents an approach to programming threshold voltages in floating-gate CMOS circuits. The threshold voltage programming is exploited in ultra low-voltage (ULV) amplifier design. A threshold voltage programming scheme is presented and several examples of analog ULV circuits are described. The ULV circuits are used in ULV amplifier design. Measured data are provided.

A Balanced Ternary Multiplication Circuit Using Recharged Semi-Floating Gate Devices

This paper presents a multiplier circuit using balanced ternary (BT) notation. The multiplier can multiply both negative and positive numbers, which is one of the advantage able properties of the balanced ternary numbering systems. By using balanced ternary notation, it is possible to take advantage of carry free multiplication, which is exploited in designing a fast multiplier circuit. The circuit is implemented with recharged semi-floating gate (RSFG) devices. The circuit operates at 1 GHz clock frequency at a supply voltage of only 1.0 Volt. The circuit is simulated by using CadenceregAnalog Design Environment, with CMOS090 process parameters, a 90nm general purpose bulk CMOS process from STMicroelectronics with 7 metal layers

A novel ternary switching element using CMOS recharge semi floating-gate devices

In this paper we present a novel voltage mode non-inverting CMOS semi floating-gate (SFG) ternary switching element. The design is applicable for reconstructing or refreshing ternary logic signals. The switching points are tuned using capacitive division. A preliminary simulation results from Cadence Spectre with AMS 0.35 /spl mu/m process parameters c35b4 is included.

Fault Tolerant CMOS Logic Using Ternary Gates

In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary and multiple-valued logic (MVL). Signals are processed through capacitors in such a way that the logic operation of a gate is independent of the DC voltage applied on the inputs. By combining signals through capacitors stuck on/stuck off and stuck at faults are not destructive when redundancy is applied. Simulated data for 130 nm and 0.35 mum CMOS processes are given.

A 0.3 V floating-gate differential amplifier input stage with tunable gain

In this paper we present a floating-Gate differential amplifier input stage with tunable gain. The input stage can be used in a differential ultra low-voltage (ULV) floating gate (FG) transconductance amplifier. Measured data for the subcircuits operating at 0.8 V, 0.5 V and 0.3 V are provided.

A novel ternary more, less and equality circuit using recharged semi-floating gate devices

This paper presents a novel ternary more, less and equality (MLE) circuit implemented with recharged semi-floating gate transistors. The circuit is a ternary application, and ternary structures may offer the fastest search in a tree structure. The circuit has two ternary inputs, and one ternary output which will be a comparison of the two ternary inputs. The circuit is a useful building block for use in a search tree application. The circuit is simulated by using Cadencereg Analog Design Environment with CMOS090 GP process parameters from STMicroelectronics, a 90 nm general purpose bulk CMOS process with 7 metal layers. The circuit operates at a 1 GHz clock frequency. The supply voltage is plusmn0.5 Volt. All capacitors are metal plate capacitors, based on a vertical coupling capacitance between stacked metal plates