Yngvar Berg

Ultra low-voltage/low-power digital floating-gate circuits

This paper describes a novel technique for implementing ultra low-voltage/low-power digital circuits. The effective threshold voltage seen from a control gate is adjusted during a UV-light-activated tuning procedure. The optimal effective threshold voltage matching the supply voltage and speed may be programmed by UV light through an activated conductance between the power rails and the floating gates. Measured results are provided for gates operating down to 0.4-V power supply, using a standard double-poly CMOS process.

Programming floating-gate circuits with UV-activated conductances

A programming technique for controlling the floating gates (FGs) in ultra-low-voltage (ULV) floating-gate circuits is presented. Simple ULV PG current-scaling and level-shifting circuits are discussed. The current scaling and level shifting are accomplished using only minimum sized transistors and floating capacitors. Floating-gate current multiplier and divider circuits are described. Measured results are provided,.

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems

In this paper we present novel recharged logic for multiple-valued (MV) systems by utilizing semi-floating-gate (SFG) transistors. The recharged multiple-valued logic can be used to implement low-power digital circuits. The improvement in power dissipation is mainly in reduced dynamic power dissipation. The main purpose is to level out the power dissipated by a digital system to obtain more suitable logic for mixed mode design.

Ultra-low-voltage floating-gate transconductance amplifiers

Ultra-low-voltage (ULV) floating-gate differential amplifiers are presented. In this paper, we present several different approaches to CMOS ULV amplifier design. Sinh-shaped and tanh-shaped transconductance amplifiers are described. Measured results are provided.

Programmable floating-gate MOS logic for low-power operation

In this paper we propose a novel technique for programming floating gate MOS transistors (FGMOS) in low-power design. By threshold-shifting low-power operation is possible with the cost of an extra polysilicon layer. Combining the FGMOS transistor with a UV-activated (UV) conductance gives rise to the UV-light programmable floating-gate MOS (FGUVMOS) transistor. The FGUVMOS transistor is utilized to increase the efficiency at low supply voltages.

An analog feed-forward neural network with on-chip learning

An analog continuous-time neural network with on-chip learning is presented. The 4-3-2 feed-forward network with a modified back-propagation learning scheme was build using micropower building blocks in a double poly, double metal 2μ CMOS process. The weights are stored in non-volatile UV-light programmable analog floating gate memories. A differential signal representation is used to design simple building blocks which may be utilized to build very large neural networks. Measured results from on-chip learning are shown and an example of generalization is demonstrated. The use of micro-power building blocks allows very large networks to be implemented without significant power consumption.

High Speed Ultra Low Voltage CMOS inverter

In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage of the evaluating transistors. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.

Ultra low voltage CMOS gates

In this paper we present a CMOS gate which operates on ultra low voltage. We show how to reduce the supply voltage Vdd to Vt without affecting the operational frequency significantly. Moreover, we elaborate on the PDP and EDP improvement compared to footed domino logic CMOS. The paper concludes with measurement from a fabricated chip in a 0.13mum process.

Area efficient circuit tuning with floating-gate techniques

An area efficient technique for tuning floating-gate circuits is described. The effective threshold voltage seen from a control gate can be programmed to virtually any value. The floating-gate transistor (FGMOS) may be used to implement low-power/low-voltage digital -and/or analog circuits.

FLOGIC-Floating-gate logic for low-power operation

In this paper we propose a novel technique for post fabrication adaptation of digital logic gates. By threshold shifting low-power operation is possible with the cost of an extra polysilicon layer. A simple MOS-transistor is used together with UV-light as a programming structure without increasing the silicon areal requirements. Initial measurements are presented.