Henry A. Nye

Electrochemical Fabrication of Mechanically Robust PbSn C4 Interconnections

Electrochemical fabrication of PbSn C4s (controlled collapse chip connection) offers significant cost, reliability, and environmental advantages over the currently employed evaporation technology. A continuous seed layer is required for through-mask electrodeposition of the solder alloy. This layer becomes the ball limiting metallurgy (BLM) for the solder pad after etching. The seed layer metallurgy and the BLM etching are crucial to obtaining mechanically robust C4s. In the present study, the issues related to the selection of seed layer metallurgy, uniformity of plating and etching, and mechanical integrity of C4s have been investigated. The results demonstrate the feasibility of electrochemically fabricating highly reliable PbSn (97/3) C4 structures with a high degree of dimensional uniformity on a variety of wafer sizes ranging up to 200 mm.

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.