Vincent J. McGahay

A high performance 0.13 /spl mu/m copper BEOL technology with low-k dielectric

The integration of dual damascene copper with low-k dielectric at the 0.13 /spl mu/m technology node is described. Up to five levels of copper wiring at three different metal pitches is provided in a spin-on organic inter metal dielectric (SiLK/sup TM/ semiconductor dielectric. The Dow Chemical Co.). Additional global wiring levels in fluorosilicate glass (FSG) at two different relaxed metal pitches result in a total of up to eight levels of hierarchical wiring for enhanced BEOL performance. Successful integration was achieved while maintaining reliability standards. Development of new advanced unit processes was required to meet the challenges presented by this work. Patterning and passivation methodologies are discussed. A key feature of the integration scheme and material set reported is the resulting reduction in complexity compared to other proposed low-k integration alternatives for the current generation.

Porous Dielectrics in Microelectronic Wiring Applications

Porous insulators are utilized in the wiring structure of microelectronic devices as a means of reducing, through low dielectric permittivity, power consumption and signal delay in integrated circuits. They are typically based on low density modifications of amorphous SiO2 known as SiCOH or carbon-doped oxides, in which free volume is created through the removal of labile organic phases. Porous dielectrics pose a number of technological challenges related to chemical and mechanical stability, particularly in regard to semiconductor processing methods. This review discusses porous dielectric film preparation techniques, key issues encountered, and mitigation strategies.

Electromigration-resistance enhancement with CoWP or CuMn for advanced Cu interconnects

Suppressing Cu diffusion along the Cu/Cap interface has proven to be one of the most effective ways to enhance the electromigration (EM) resistance of advanced Cu interconnects. Two methods, depositing a thin layer of CoWP on the Cu surface and doping the Cu seed layer with Mn, are presented in this paper. While each effectively enhanced the EM performance, they behaved somewhat differently in improving the line-depletion and via-depletion EM performance. CoWP functioned primarily as a Cu surface modifier and did not alter the Cu diffusion behavior below the surface, making Cu interconnects capped with CoWP very sensitive to defects in the via. As a result, the hardware processed with CoWP had greatly increased EM failure times, but also had large variability in failure times and activation energy. On the other hand, the hardware with the CuMn seed layer relied on Mn segregation to the Cu surface to slow down the Cu diffusion, plus Mn also may have diffused to grain boundaries and defective areas of the liner. Although the EM failure times of Cu interconnects with CuMn seed in some cases were not as long as those with CoWP, the variability and sensitivity to process defects was reduced.

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

The 45-nm technology, called 12S and developed for IBM POWER7®, is an extremely robust and versatile technology platform that allows for a rich set of features that include embedded dynamic random access memory (DRAM), performance and dense static RAM (SRAM), a trench-based decoupling capacitor, a comprehensive device menu, and a high-performance hierarchical back-end interconnect scheme, all built on a silicon-on-insulator (SOI) substrate. Embedded DRAM was implemented for production in high-performance SOI for the first time and allowed us to leapfrog two generations of conventional SRAM densities. Immersion lithography was also employed for the first time in 45-nm IBM products. Our 45-nm design point represents a judicious leverage of silicon oxynitride dielectrics, scaled device technology, and rich features to yield chip-level performance enhancement of more than 50%, compared with our 65-nm node at comparable or less power. This paper describes the salient features of this technology node, the process architecture, the device design rationale, and the process design interactions.

Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric

The reliability of a stacked via chain stressed under various thermal cycle conditions is described. The chain consists of Cu Dual Damascene metallization with SiLK (trademark of Dow Chemical) as the organic low-k dielectric. Failure analysis indicates that cracks form in the Cu vias during thermal cycle stress. Due to the presence of two failure modes, the thermal cycle statistical behavior is described by a bimodal lognormal failure distribution. The thermal cycle lifetime exhibits a strong dependence on the temperature range and a rather weak dependence, on the maximum temperature in the cycle. Evidence of a threshold temperature range below which thermal cycle fails should not occur as well as a correlation between the test structure yield and reliability are also reported.

High-current characterization of dual-damascene copper interconnects in SiO/sub 2/- and low-k interlevel dielectrics for advanced CMOS semiconductor technologies

The ESD robustness of copper (Cu) interconnects in low-k interlevel dielectrics (ILD) is shown for the first time. Critical-current density to failure J/sub crit/, high-current resistance change /spl Delta/R/R/sub o/, and thermal impedance /spl theta//sub TH/ are determined for Cu-based interconnects with silicon dioxide (SiO/sub 2/) and low-k interlevel dielectrics. Experimental results indicate that ESD robustness of Cu-based interconnects in low-k ILD (k=2.9) is affected by low-k material (compared to Cu wires in SiO/sub 2/ ILD), yet have superior ESD robustness compared to Al-based interconnects.

Geometry, kinetics, and short length effects of electromigration in Mn doped Cu interconnects at the 32nm technology node

Mn doping in Cu seed has been used to improve EM performance at the 32nm technology node. This paper will show that on an optimized process with CuMn there were different degrees of EM enhancement for geometric variations including line width and electron flow direction. In addition, kinetics experiments on several geometries resulted in activation energies in the range of 0.95-1.33eV. Finally, the Blech threshold (jL)c=338mA/um was derived from the experimental data on various line lengths and current densities.

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.

BEOL Integration of Highly Damage -Resistant Porous Ultra Low-K Material Using Direct CMP and Via-first Process

We have demonstrated porous ultra low-K (ULK)/Cu interconnect integration using via first integration scheme and a direct ULK CMP process. The key features of the damage-resistant porous ULK material were novel material chemistry, a higher carbon concentration (15.4 atm%) and an improved pore structure. These improved features of the new ULK material enabled superior process-induced dielectric material damage during patterning etch, resist strip, and ULK direct CMP. Interconnect structures fabricated using the conventional ULK material showed high short leakage currents and open failures due to moisture uptake. The integrated structures of the new, robust porous ULK material exhibited good electrical properties. The target capacitance values have been achieved for future porous ULK/Cu interconnects

Integration of copper and fluorosilicate glass for 0.18 /spl mu/m interconnections

The integration of dual damascene copper with fluorosilicate glass (FSC) at the 0.18 /spl mu/m technology node is described. The BEOL structure has been implemented for an advanced CMOS technology, and along with an SOI FEOL is being used for high performance logic and SRAM devices. Reliability and yield is shown to be equivalent to a similar technology without FSG. Key considerations in the development of this technology are presented.