Christopher V. Jahnes

Microstructured magnetic tunnel junctions (invited)

We have used a simple self-aligned process to fabricate magnetic tunnel junctions down to submicron sizes. Optical and electron-beam lithographies were used to cover a range of areas spanning five orders of magnitude. The bottom magnetic electrodes (Co or permalloy) in our junctions were exchange biased by an antiferromagnetic layer (MnFe). The top electrodes were made of soft magnetic materials (Co or permalloy). We have consistently obtained large magnetoresistance ratios (15%–22%) at room temperature and in fields of a few tens of Oe. The shape of the field response of the magnetoresistance was varied from smooth to highly hysteretic by adjusting the shape anisotropy of one junction electrode.

Non-blocking 4x4 electro-optic silicon switch for on-chip photonic networks

We present a 4x4 spatially non-blocking Mach-Zehnder based silicon optical switch fabricated using processes fully compatible with standard CMOS. We successfully demonstrate operation in all 9 unique switch states and 12 possible I/O routing configurations, with worst-case cross-talk levels lower than -9 dB, and common spectral bandwidth of 7 nm. High-speed 40 Gbps data transmission experiments verify optical data integrity for all input-output channels.

The respective role of oxygen and water vapor on the tribology of hydrogenated diamond-like carbon coatings

The tribological behavior of diamond-like carbon coatings (DLC) strongly depends on the chemical nature of the test environment. The present study proposes to explore the influence of water vapor and oxygen on the friction behavior of a hydrogenated DLC coating exhibiting ultralow friction in ultrahigh vacuum (friction coefficient below 0.01). Using a UHV tribometer, reciprocating pin-on-flat friction tests were performed in progressively increasing or decreasing partial pressures of pure oxygen and pure water vapor. The maximum gaseous pressures of oxygen and water vapor were 60 hPa and 25 hPa (1 hPa = 100 Pa), respectively, the second value corresponding to a relative humidity (RH) of 100% at room temperature. It was found that, for the pressure range explored, oxygen does not change the ultralow friction behavior of DLC observed in UHV. Conversely, water vapor drastically changes the friction coefficient at pressures above 0.5 hPa (RH = 2%), from about 0.01 to more than 0.1. Electron energy loss spectroscopy and in situ Auger electron spectroscopy have been performed to elucidate the friction mechanisms responsible for the tribological behaviors observed with the two different gaseous environments. In all cases no significant oxidation has been observed either inside the wear scars or in the wear debris particles. Ultralow friction is systematically associated with a homogeneous carbon-based transfer film. The higher friction observed at partial pressure of water vapor higher than 0.5 hPa, is associated with a thinner transfer film. Consequently friction seems to be controlled by the transfer film whose kinetics of formation strongly depends on the partial pressure of water vapor.

2.5D and 3D technology challenges and test vehicle demonstrations

Three-dimensional (3D) chip integration with through-silicon-vias (TSVs) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSVs and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSVs and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges include wafer integration and finishing with TSVs, test for known-good-die (KGD), assembly and module integration. Infrastructure compatibility and use of newly evolving industry standards such as Semi-3D standards for wafer handling and JEDEC standards for wide I/O memory to name two examples. Standards for wafer shipping are underway and other 3D compatibility standards are being defined over time. This research paper describes key challenges to enable systems using 2.5D and 3D technology. The paper also highlights progress and results for 2.5D and 3D hardware demonstrations and gives an outlook on future demonstrations.

Wear-resistant fluorinated diamondlike carbon films

Fluorinated diamondlike carbon (FDLC) films have been deposited on Si wafers by rf plasma-assisted chemical vapor deposition, under a variety of conditions. The films have been characterized by FTIR and index of refraction measurements, RBS and FRES analysis for determination of film composition, and stress measurements from the bending of the wafers by the deposited films. Friction and wear measurements have been performed using pin-on-flat and pin-on-disk testers in ambient air, at maximum Hertzian contact pressures ranging from 320 to 1100 MPa. By adjusting the deposition parameters, the properties of the FDLC films could be changed from soft films, with no significant wear resistance, to films containing more than 20% F and having wear resistance comparable to unfluorinated DLC. The tribological properties of the FDLC films are discussed in relation to their physical properties, as determined by the deposition conditions.

Novel Low k Dielectrics Based on Diamondlike Carbon Materials

Hydrogenated diamondlike carbon (DLC) and fluorine containing DLC (FDLC) were investigated for their potential applications as low k dielectrics for the back end of the line interconnect structures in ultralarge scale integrated circuits. It was found that the dielectric constant (k) of DLC can be varied between 3.4 by changing the deposition conditions. The thermal stability of the DLC films was found to be correlated to the values of the dielectric constant, decreasing with decreasing k. Only DLC films having dielectric constants k > 3.3 appeared to be stable to anneals of 4 h at 400°C in a nonoxidizing environment. However these films were characterized by stresses higher then 600 MPa. FDLC films, thermally more stable at 400°C than the DLC films with k > 3.3, could be prepared with dielectric constants below 2.7 and internal stresses <200 MPa. Such FDLC films are thus promising candidates as a low k interconnect dielectric.

High‐frequency permeability of laminated and unlaminated, narrow, thin‐film magnetic stripes (invited)

The permeability of the magnetic material in a thin‐film magnetic head is an important, but hard to characterize, parameter since the magnetic permeability depends on the head domain structure, the drive frequency, and the shape and size of the head. We have measured the high‐frequency permeability from 1 MHz to 300 MHz, hysteresis loops, and domain structure of unlaminated and multilayer magnetic thin‐films as a function of stripe width for arrays of long narrow stripes. Monolithic permalloy films and permalloy films laminated with SiO2 have been photolithographically patterned and ion‐milled to create 3 to 1000 μm wide rectangles, 1 cm long, with the hard axis oriented along the long axis of the rectangles. The high‐frequency permeability of each array of a given width is measured by the signal detected by a nonresonant butterfly‐coil pickup loop when the film is driven by a uniform radio‐frequency magnetic field generated by a strip‐line waveguide. The changes in domain pattern as the film structure an...

Monolithic spiral inductors fabricated using a VLSI Cu-damascene interconnect technology and low-loss substrates

This paper presents spiral inductor structures optimized in a Cu-damascene VLSI interconnect technology with use of silicon, high-resistivity silicon (HRS), or sapphire substrates. Quality factors (Q) of 40 at 5.8 GHz for a 1.4 nH-inductor and 13 at 600 MHz for a 80 nH-inductor have been achieved.

Pitting of Sputtered Aluminum Alloy Thin Films

Etude de la corrosion par piqure des alliages Al−Ti et Al−Cr dans une solution saline de NaCl

Reactive magnetron sputtered zirconium oxide and zirconium silicon oxide thin films

Thin films of ZrO2 and ZrO2–SiO2 were deposited by reactive dc magnetron sputtering. The optical properties, density, microstructure, and crystalline phase of pure ZrO2 films were found to be a function of deposition rate. In particular, the index of refraction could be varied from 1.77 to 2.13 by increasing the deposition rate from 11 to 720 A/min. The density of the films increased from 3.9 to 5.8 g/cm3 over the same deposition rate range. Small amounts of SiO2 (10 at. %) stabilized the mixed films in an amorphous phase. A linear relationship between index of refraction and SiO2 content was observed and, as in the case of pure ZrO2, increasing deposition rate resulted in mixed films with higher densities and indices for a fixed SiO2 content. The structure and optical properties of the mixed films remained unchanged with thermal cycling up to 500 °C.