Henry K. Utomo

Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates

CMOS devices with embedded SiGe source/drain for pFETs and tensile stressed liner for nFETs have been demonstrated for the first time on hybrid orientation substrates. Ring oscillators have also been fabricated. Significant performance improvement is observed in hybrid orientation substrates compared to (100) control substrates with embedded SiGe.

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

An aggressively scaled high performance 45 nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45 nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at IV, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.

High performance bulk planar 20nm CMOS technology for low power mobile applications

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 μA/μm at Ioff = 10 nA/μm at VDD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region, the parasitic short-channel effects due to this fin tail have been successfully suppressed. We further demonstrate the extension of the BOTS process to the fabrication of strained SiGe FinFETs and nanowires, providing a path for future CMOS technologies.

Higher hole mobility induced by twisted Direct Silicon Bonding (DSB)

Twisted direct silicon bonded (DSB) substrate demonstrates a higher hole mobility advantage over (110) bulk substrate for PFET. The mobility shows a (110) layer thickness dependence with the thinner DSB layer having a higher hole mobility. 25% on-current improvement is obtained for thin DSB PFETs at long channel (Lg= 2 mum), 10% higher at short channel (Lg = 36 nm) compared to (110) bulk PFETs. Moreover, we found that the thinner DSB shows better Vt roll-off characteristics. On the other hand, NFETs on DSB are as good as (100) bulk NFETs. Thin DSB substrate demonstrates 11% faster ring oscillator speed over thick DSB substrate and 30% faster over (100) bulk due to higher mobility and lower capacitance.

NiSi Roughness on Embedded SiGe

. Introduction Ni silicide has been considered as promising salicide process in below 65nm CMOS technology due to low Rs and lower thermal budget than Co silicide. Recently embedded SiGe(eSiGe) process has been widely developed to enhance pFET performance by hole mobility improvement. However, Ni silicidation on eSiGe showes several issues that need to be solved. One of them is bad roughness in between Ni silicide and eSiGe interface. Interface roughness caused by non-uniform silicide thickness on eSiGe is very susceptible to junction leakage current in source/drain (S/D) area and should be well controlled as the ground rule shrinks down. In this study, effects of pre amorphization implantation (PAI) and in-situ Si capping on top of eSiGe were examined to improve Ni silicide interface roughness.