Emre Alptekin

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

High performance bulk planar 20nm CMOS technology for low power mobile applications

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

Interconnect performance and scaling strategy at the 5 nm Node

In this paper, major challenges for 5 nm node BEOL performance are presented. High wire resistance is a key issue for interconnect delay. Accordingly, we focus on potential wire resistance reduction with various architectures and materials. Copper liner thickness was identified as the major knob for increasing Cu areal percent, as compared to increased line aspect ratio and width. Interconnect delay variability is reviewed and analyzed with respect to various patterning techniques.In this paper, optimization of 1X BEOL wiring level of 7 nm node is presented. We focus on the interconnect delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on the characteristics of the 10 nm driver circuit. Then the result is compared with a shrunk version of the circuit at the 7 nm dimension. Therefore, the impact of the BEOL on the circuit performance can be determined. The interconnect delay is plotted as a function of wire resistance, via resistance and capacitance. In order to better optimize the BEOL architecture, contour plots of resistance versus capacitance are presented in this paper. The result of this paper is indicating a strong dependency of circuit performance on the wiring length which is a new challenge. Optimization of BEOL architecture therefore requires a new approach which is outlined in this paper. As a result, we would like to bring this to the design communitys attention.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

Understanding short channel mobility degradation by accurate external resistance decomposition and intrinsic mobility extraction

An intrinsic short channel mobility extraction method is proposed by measuring two short-channel devices with different channel lengths and the same source/drain and contact geometry. The constant and dynamic components of external resistance are separated. Short-channel mobility degradation is observed and its origin is studied. The possible causes of the halo doping and the non-uniformity of the inversion layer charge are accounted for. The weaker temperature dependence of short channel devices indicates that the short channel mobility degradation may result from some combination of defect-induced and Coulomb-induced scattering near the S/D regions, differing in severity between NFETs and PFETs which employ, respectively, ion implant and embedded epitaxy as the primary component of S/D design.

10nm FINFET technology for low power and high performance applications

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

Gas cluster ion beam assisted NiPt germano-silicide formation on SiGe

We report the formation of very uniform and smooth Ni(Pt)Si on epitaxially grown SiGe using Si gas cluster ion beam treatment after metal-rich silicide formation. The gas cluster ion implantation process was optimized to infuse Si into the metal-rich silicide layer and lowered the NiSi nucleation temperature significantly according to in situ X-ray diffraction measurements. This novel method which leads to more uniform films can also be used to control silicide depth in ultra-shallow junctions, especially for high Ge containing devices, where silicidation is problematic as it leads to much rougher interfaces.

Precleans challenges on middle-of-the-line contacts for 14nm technologies and beyond

In-situ dry cleans of silicon-based surfaces preceding the metallization process step have a crucial impact on contact resistance, yield and reliability of middle-of-the-line (MOL) local interconnects. Existing precleaning techniques meet numerous challenges predominantly originated from reduced device geometries such as critical dimensions enlargements, epitaxial junctions gouging and insufficient native oxide removal. Reactive chemical cleans employing remote plasma assisted with NF3/NH3 gas mixtures designated as SiCoNi™ include complex etchant-surface interactions. This report discusses junction-to-metal interfacial aspects of physical and chemical precleans applied to MOL contacts. The fundamental mechanisms that govern clean efficiency of MOL contacts are analyzed in order to insure the manufacturability of defect-free local interconnects.