Henny Volders

A new perspective of barrier material evaluation and process optimization

A novel test structure based on a planar capacitor design has been used for advanced barrier material evaluation and process optimization. This structure enables intrinsic reliability study of Cu/low-k interconnects. Various barrier materials such as CuMn self-forming barrier, ALD Ru, and PVD TaNTa on different dielectric films have been investigated to understand their intrinsic limits of barrier performance. The learning generated from the novel test structure has been directly used for barrier optimization of dual damascene processes.

Copper Plating on Resistive Substrates, Diffusion Barrier and Alternative Seed Layers

We have studied electrochemical deposition of copper on ruthenium-tantalum (Ru-Ta) alloy, tantalum (Ta), and cobalt (Co) substrates using cyclic voltammetry and galvanostatic methods. We show that a single-step direct-plating from acidic Cu bath approach is favorable on thin Ru-Ta films, while it presents a significant challenge for plating on resistive Ta and Co substrates.

Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)

Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).

CMP process optimization for improved compatibility with advanced metal liners

As copper interconnect structures are shrinking with each technology node novel metals other than PVD Ta(N)/Ta are being introduced as barrier materials. These materials act as seed enhancement layers and enable the Cu filling of the narrowest structures. However, the integration of such metals into the manufacturing of sub-35 nm wide Cu lines produces several challenges which need to be addressed. One of these challenges is the compatibility of the interconnect metals with the copper Chemical Mechanical Polishing (CMP) step. In particular, corrosion issues and Cu defectivity in the trenches need to be controlled. An evaluation of the compatibility of the CMP slurries with the new incorporated materials therefore becomes extremely important. Our work shows that by optimizing the CMP process and selecting compatible slurries, novel metals such as CVD Co (combined with a Ta(N) barrier) are promising candidates for the metallization of sub-35 nm lines.

Dielectric Reliability of 50 nm Half Pitch Structures in Aurora® LK

The dielectric reliability of Aurora® LK (k = 3.0) material has been evaluated on a 50 nm half pitch test structure. These were fabricated using a double patterning scheme and TiN metal hard mask. The introduction of a suitable post-etch residue removal step and close-coupled processing between Cu electroplating and chemical mechanical polishing were found to be key for achieving high yield. Median time-dependent dielectric lifetime of 10 years is reached at an electrical field of 1.4 MV/cm, comparable to earlier reported results with SiO2 as dielectric. The reliability performance is found to be significantly layout dependent with corners being weak points due to local field enhancement.

Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora® LK HM

Aurora® LK HM (k=3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora® LK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of the physical vapor deposition (PVD) based barrier/seed process and adjusting of the barrier chemical mechanical polishing (CMP) overpolish condition were yield enabling factors. No degradation of the breakdown field upon reducing half pitch is observed down to 30 nm for line lengths up to at least 1 mm. The median time-dependent dielectric breakdown (TDDB) lifetime, as evaluated on a 1 mm 35 nm half pitch parallel line structure, exceeds 10 years at an electrical field of 2.6 MV/cm.

Metallization of sub-30 nm interconnects: Comparison of different liner/seed combinations

Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.

Cu Resistivity Scaling Limits for 20nm Copper Damascene Lines

Two of the most important questions concerning the future of interconnects are 1) how scalable is the damascene process to extremely narrow trenches and 2) what is the resistivity of Cu in these trenches? We attempt to answer both these questions through the generation of high aspect ratio, rectangular cross section trenches as narrow as 20 nm using a novel sacrificial Si FIN process flow. To fill such aggressive geometries, we also explore advanced PVD and ALD barrier and seed processes. We find significant electrical yields for 25 to 35 nm test structures with resistivities as predicted by sidewall scattering models.