Hichem M'Saad

Materials and processing for 0.25 mm multilevel interconnect

A new generation of interconnect schemes is required for high performance ULSI. This involves developing process modules aimed at reducing RC delay and power consumption, as well as developing new equipment technology to support these processes. In the materials area, the most significant challenge is to define a workable and reliable combination of high conductivity metals (Al(Cu), Cu) with a low dielectric constant insulator (starting with fluorinated silicon oxide). As far as processing is concerned, the key technological issues that we will address in this paper are (i) etching dielectrics and metals with high aspect ratio (4:1 for contact/via and greater than 1.5:1 for lines/trenches) and (ii) filling these aggressive topologies using dielectric films with high gap-filling capabilities and conformal/planarizing CVD and PVD metal deposition. Besides the option of using SiOF dielectric and oxide CMP, four process modules of interconnects can be highlighted: (1) gap-fill oxide/W interconnect and/or via plug/metal etch; (2) gap-fill oxide/via fill and planarized Al/metal etch; (3) metal plug/metal damascene; and (4) Cu dual damascene. Since time-to-market will still be very critical for fabrication at 0.25 μm technology, typically for 200 mm and 300 mm wafers, the challenge is clearly to achieve successful vertical and horizontal integration of these modules. As a result, more than ever, suppliers and chip manufacturers have to work very closely at early stages of technology development. Examples of joint development programs leading to new breakthroughs in technology and reactor design will be discussed.

Integration of a stack of two fluorine doped silicon oxide thin films with interconnect metallization for a sub-0.35 /spl mu/m inter-metal dielectric applications

Stable fluorine doped PETEOS and HDP-CVD silicon oxide thin films have been deposited without any capping layer. Gap-filling of 0.35 /spl mu/m metal spacing (2:1 A.R.) has been studied, and partial integration has been successfully achieved.

Plasma-induced defect generation on silicon surfaces in HDP-CVD processing

The impact of the HDP-CVD process on Si surfaces has been studied. It has been shown that the sputter component in the process enhances the features and the detection of Si surface defects. These defects, 0.16-0.30 /spl mu/m in size, are correlated to other characterization techniques such as capacitance-voltage measurements, plasma damage monitoring, and photoconductance decay spectroscopy. We show that these defects are a result of the interaction between the energetic ions in the deposition process and the crystal-originated voids during the Czochralski crystal growth. We show how these defects can be modulated among different processing conditions. The learning has been applied to optimizing the initial steps of plasma deposition in the HDP-CVD process for shallow trench isolation and pre-metal dielectric applications. This work also underscores the importance of applying low information content sensors to the early detection and control of plasma damage in high density plasma applications.

Film properties and integration performance of a nano-porous carbon doped oxide

A porous carbon doped oxide has been developed using a conventional PECVD reactor. Sequential electron beam treatment using a flood beam provides a means for removal of the thermally labile organic species and results in a porous material with high thermal stability. Film properties and integration results presented show the viability of integrating this film into a conventional dual damascene interconnect flow.

Reliability of dielectric barriers in copper damascene applications

The film properties of two PECVD deposited dielectric copper barrier films have been optimized to improve BEOL device reliability in terms of electromigration. Two critical aspects that affect electromigration are the dielectric barrier film hermeticity and adhesion to copper. We use a method to quantify the barrier film hermeticity of the BLO/spl kappa/ I low-/spl kappa/ dielectric film to be similar to that of silicon nitride. In addition, the interfaces between damascene nitride with copper, as well as BLO/spl kappa/ I with copper have been engineered to improve the interfacial adhesion energy to >10 J/m/sup 2/ for both damascene nitride and BLO/spl kappa/ I.

Post Deposition Ultraviolet Treatment of Silicon Nitride Dielectric: Modeling and Experiment

Simulation and FTIR analysis of the UV treatment impact on bond strengths of PECVD deposited silicon nitride films

Reliability of Dielectric Barrier Films in Copper Damascene Applications

The film properties of two PECVD deposited dielectric copper barrier films have been optimized to improve BEOL device reliability in terms of electromigration. Two critical aspects that affect electromigration are the dielectric barrier film hermeticity and adhesion to copper. We use a method to quantify the barrier film hermeticity and have optimized the hermeticity of the BLOκ™ low-κ dielectric barrier film to be similar to that of silicon nitride. By using FT-IR we find that the film porosity has a much stronger effect than the film stoichiometry on hermeticity. In addition, the interfaces between Damascene Nitride™ with copper, as well as BLOκ with copper have been engineered to improve the interfacial adhesion energy to >10 J/m2 for both Damascene Nitride and BLOκ.

Advanced PECVD-Based Anti-Reflective Coating for 90nm Generation Interconnects

A plasma-enhanced chemical vapor deposition-based nitrogen-free dielectric anti-reflective coating was successfully developed for use in 90nm interconnects in conjunction with low κ materials. By choosing N-free precursors, it was possible to eliminate any adverse interactions between the NH 2 amine group and the DUV 193nm photoresist that is directly in contact with the anti-reflective coating (ARC), thus eliminating major source of photoresist poisoning-induced footing. N-free dielectric ARC demonstrated a wide tunable range of its optical properties at 193nm in a single wafer PECVD reactor: 1.6 in-situ deposition of a dual-layer dielectric ARC on the low λ dielectric layers during the dual damascene process. The dual-layer coating, which consists of a phase-shift layer on an absorbing layer, can keep the substrate reflectivity below 1% across the wafer, minimizing CD swing. N-Free dielectric ARC can be easily integrated with low κ dielectrics. Its adhesion with low κ materials is excellent and it can be etched and chemically and mechanically polished together with low κ dielectrics.

HDP-FSG Integration in Multilevel Interconnect Devices

HDP-FSG has been integrated as an inter-metal dielectric in a multilevel interconnect scheme. Process regimes for obtaining stable HDP-FSG films were identified. Gap-fill of high aspect ratio structures was achieved for 0.18µm technology node. HDP-FSG film stability, homogeneity, and impurity content were evaluated. In addition to the development of the HDP-FSG process, integration of the interconnect module was investigated and optimized. Analysis of the AI/FSG interface integrity was tested for gap-fill and corrosion with SEM and for fluorine diffusion with SIMS. CMP rate of the FSG was determined and compared to HDP-USG. Al metallization integration approaches in conjunction with FSG were identified.

Resist Poisoning-Free Advanced PECVD-Based Anti-Reflective Coating (ARC) for 90nm Technology and Beyond

A nitrogen-free (N-free) dielectric anti-reflective coating (DARC®) was cost-effectively developed in a plasma-enhanced chemical vapor deposition (PECVD) reactor to eliminate the 193nm resist poisoning interaction caused when N 2 O is used as a precursor [1]. Although it was found that even a N-free ARC could poison sensitive 193nm resists with –OH radicals [2], which either exist inherently in the ARC or result from H 2 O absorption by the ARC surface, the current investigation has revealed that it was possible to minimize resist poisoning. Our investigation showed that compressive film stress directly correlates to H 2 O resistance. Therefore, it was possible to greatly improve the ARC resistance to H 2 O absorption by creating and maintaining a process regime that makes the ARC film dense. The dense ARC film demonstrated promising lithography performance with minimal resist poisoning as well as excellent shelf life and O 2 -ashing resistance. This paper explores the N-free DARC material, its development, lithographic integration results and implementation in a production environment to eliminate 193nm resist poisoning.