Hitoshi Kume

Submicrometer MOSFET structure for minimizing hot-carrier generation

This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO 2 energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.

Read-disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memories

This paper describes the degradation of read-disturb characteristics related to time-dependent current caused by electron trapping in tunnel-oxide film. The time-dependent current, rather than the stress-induced leakage current, affects the threshold-voltage shift in memory cells with relatively thick tunnel oxide (>7 nm) and long disturbance time. Programming and erase endurance affects read disturb such that the read-disturb lifetime is improved in memory cells with nitrided oxide which exhibit long-endurance characteristics.<<ETX>>

An As-P(n + -n - )double diffused drain MOSFET for VLSI's

An As-P(n+-n-) double diffused drain is characterized as one of the most feasible device structures for VLSIs from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.

A flash-erase EEPROM cell with an asymmetric source and drain structure

A flash-erase EEPROM cell which consists of a single floating gate transistor is described. The cell is based on self-aligned double polysilicon stacked gate structure without a select transistor. It is programmed and erased by hot electrons at the drain edge similar to a UV-EPROM, and by Fowler-Nordheim tunneling of electrons from the floating gate to the source, respectively. An asymmetry in source and drain regions is introduced to enable fast program/erase operation. In addition, an n+concentration in the source region is optimized to achieve reproducible erasure, which is indispensable to avoid over-erasing problem. The optimized cell enables an erasing time of less than one millisecond with 12. 5 V on the source, and a scatter of erased Vth is almost negligible. Endurance and data retention characteristics is also adequate for implementation in memory chips. The small cell area of 9.3µm2is accomplished in a 0.8µm technology.

Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM

The impact of a random telegraph noise (RTN) on a scaled-down SRAM is shown for the first time. To estimate the impact on SRAM, we statistically analyzed a threshold voltage fluctuation (DeltaVth) of n-and p-MOSFETs. It is revealed that DeltaVth of the p-MOSFET is larger than that of the n-MOSFET. This difference can be explained by considering the followings: (i) number- and mobility-fluctuation models of RTN (ii) the difference in the capture cross section between electron and hole. In addition, based on these results, SRAM margin enclosed by read / write Vth curves with or without RTN was simulated. We consequently found that Vth margin comes close to Vth window of the SRAM by considering the effect of RTN on DeltaVth, even at hp 65. Moreover, DeltaVth due to RTN of the p-MOSFET is comparable with DeltaVth due to the random dopant fluctuation (RDF) at hp 45 because DeltaVth due to the RDF is inversely proportional to square root of the gate area (S), while DeltaVth due to RTN is inversely proportional to S.

A novel MNOS technology using gate hole injection in erase operation for embedded nonvolatile memory applications

A novel MNOS memory with gate hole injection in erase operation has been demonstrated for embedded nonvolatile memory applications. Superior characteristics with 10/spl mu/sec programming and 10msec erasing speed were obtained as compared with conventional MONOS structures. In addition, we found that the localized interface trap at source side region was generated by excess holes during erasing cycle and could be suppressed by Lg scaling. This result shows the good scalability of this technology.

Analysis of detrap current due to oxide traps to improve flash memory retention

To improve flash memory retention characteristics, we study detrap current due to oxide traps in metal-oxide-semiconductor structures (MOS capacitors and MOSFETs). We show that threshold voltage shift due to detrap current in flash memories can reach 0.6 V for 1 year. This value is detrimental for flash memory retention. Next, we analyze the two types of conduction mechanism of the detrap current, which are direct tunneling to the anode from deeper traps and thermally excited electron tunneling to the oxide conduction band from shallower traps. The deeper traps are generated by electron injection during Fowler-Nordheim stressing, while the shallower traps are generated by hole injection.

A 256 Mb multilevel flash memory with 2 MB/s program rate for mass storage applications

A 256 Mb flash memory in 0.26 /spl mu/m CMOS on a 138.6 mm/sup 2/ die uses a multilevel technique. The AND-type memory cell suitable for multilevel operation is used. One sector consists of(8192+256) memory cells. As two bits of data are stored in one physical cell, logical sector size is (16384+512)b. Sector erase and program times are both 1 ms/sector (2048+64B), so typical programming rate is 2 MB/s. By increasing sector size to four times that in conventional two-level flash memories, program throughput is kept acceptable for mass-storage applications, even with multi-level operation.

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories

This paper proposes circuit technologies adaptable to the potential scalability of flash memory cells and an accurate internal voltage generator for use under low voltage operation. A circuit with a relaxed layout pitch, bit-line clamped sensing multiplex, and intermittent burst data transfer (four phases with 500 ns/20 ns) is proposed for a three times feature-size pitch. A 5-/spl mu/A low-power dynamic band-gap generator with voltage boosted by using triple-well bipolar transistors and voltage-doubler charge pumping, for accurate generation of 10 to 20 V, are also proposed for use at V/sub vv/ of under 2.5 V. To demonstrate the circuit feasibility, a 105.9-mm/sup 2/ 128-Mb experimental chip was fabricated using 0.25-/spl mu/m technology.

A new data retention mechanism after endurance stress on flash memory

We propose a new data retention model after endurance stress that may be explained as a combination of two retention mechanisms. One inherent retention characteristic is ruled by thermionic emission and is dominant above 150 C. The other retention mechanism is dominant below 85 to 125 C and is controlled by anomalous SILC. We have clarified that the data retention properties after P/E cycling were well fitted by the hopping conduction model. In particular, the presence of traps generated by excessive P/E cycling played a significant role in the temperature dependence of the retention lifetime.