Katsutaka Kimura

Read-disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memories

This paper describes the degradation of read-disturb characteristics related to time-dependent current caused by electron trapping in tunnel-oxide film. The time-dependent current, rather than the stress-induced leakage current, affects the threshold-voltage shift in memory cells with relatively thick tunnel oxide (>7 nm) and long disturbance time. Programming and erase endurance affects read disturb such that the read-disturb lifetime is improved in memory cells with nitrided oxide which exhibit long-endurance characteristics.<<ETX>>

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

A precise on-chip voltage generator for gigascale DRAMs with a negative word-line scheme is described. It combines a charge-pump regulator and a series-pass regulator, and it also includes a positive and negative offset voltage generator that uses a bandgap generator with a differential amplifier. The proposed circuit was experimentally evaluated with a test device fabricated using a 0.3-/spl mu/m process. The simulation results show that the series-pass regulator suppresses the noise on a word-line low voltage (negative) to below 30 mV for the word-line transient and V/sub BB/ bouncing. A dc-voltage error of less than 6% without trimming is confirmed for the positive and negative offset voltage generator through the test device. These results show that the described scheme can be used in future low-voltage gigascale DRAMs.

Power Reduction Techniques in Megabit DRAM's

Power dissipation in dynamic random-access memories (DRAMs) is described. Power reduction techniques are summarized and a comparison is made of NMOS and CMOS for individual circuits focusing on power dissipation for full- V/sub cc/ precharge and half- V/sub cc/ precharge, decoder, and clock generator. These results are then applied to actual 1-Mbit chips. The CMOS approach with a half-V/sub cc/ precharge is found to result in a power dissipation of just half that for NMOS, which is, verified through experiments on 1-Mbit CMOS and NMOS chips. Furthermore, from estimating power dissipation for DRAM chips larger than 1 Mbit, it is thought that the critical point for power-supply transition from the existing 5 V is around the 16-Mbit level.

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories

This paper proposes circuit technologies adaptable to the potential scalability of flash memory cells and an accurate internal voltage generator for use under low voltage operation. A circuit with a relaxed layout pitch, bit-line clamped sensing multiplex, and intermittent burst data transfer (four phases with 500 ns/20 ns) is proposed for a three times feature-size pitch. A 5-/spl mu/A low-power dynamic band-gap generator with voltage boosted by using triple-well bipolar transistors and voltage-doubler charge pumping, for accurate generation of 10 to 20 V, are also proposed for use at V/sub vv/ of under 2.5 V. To demonstrate the circuit feasibility, a 105.9-mm/sup 2/ 128-Mb experimental chip was fabricated using 0.25-/spl mu/m technology.

A giga-scale assist-gate (AG)-AND-type flash memory cell with 20-MB/s programming throughput for content-downloading applications

Proposes a new AND-type flash memory cell with an assist gate (AG), which has achieved a 20-MB/s programming throughput. For high-speed parallel programming on the order of kilobytes, fast cell programming (10 ps) and an extremely low channel current (I/sub ds/ /spl les/ 100 nA/cell) are necessary. These features were achieved by using the low current source-side injection method in which the AG was used as a program gate. The memory cell size has also been reduced to 0.104 /spl mu/m/sup 2/ by taking advantage of an AG using field isolation and a self-aligned floating gate. These technologies are the keys to giga-scale flash memories, of which the main application is content downloading.

A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse

To cope with difficult device miniaturization in the multi-gigabit era, memory cells smaller than the traditional 8F/sup 2/ folded bitline (BL) cell are needed. A 6F/sup 2/ trench capacitor folded-BL cell has been recently described. However, it needs not only additional tight-pitch layers to create a vertically folded-BL arrangement, but also a vertical transistor. The 6F/sup 2/ open-BL cell enabling a simple planar transistor is another candidate as its inherently large imbalance noise between pairs of BLs is reduced. Low-voltage, high-speed array operation is essential in the multi-gigabit era. A conventional non-over-driven sensing scheme cannot achieve a high enough speed at an array voltage below 1.6 V, because the threshold voltage (Vth) cannot be reduced <0.1 V to obtain a low enough stand-by current. Distributed over-driven sensing enables a higher speed due to reduced voltage loss caused by distributed drivers combined with meshed power lines. Consequently, compared with the conventional schemes, the sensing time for a 1.2 V array voltage necessary for the 1 Gb generation decreased by 6.9 ns and 2.0 ns. Hence, this sensing scheme is promising for array voltages below 1.0 V in multi-gigabit memory. In multi-gigabit DRAMs, redundancy for degraded cells after packaging is a major concern. To overcome this a scheme is adopted which features a stacked flash fuse composed of three series flash fuses utilizing standard CMOS transistors without any additional process steps. Thus this technology can be used to fabricate a 0.13 μm 180 mm/sup 2/ 1 Gb DRAM assembled in a 400-mil package.

A Block-oriented Ram With Half-sized Dram Cell And Quasi-folded Data-line Architecture

The authors describe a block-oriented random-access memory (BORAM) based on a series-connected cell concept and a quasi-folded data-line architecture. The series-connected cell concept allows a nearly half-sized DRAM cell even when using the same fabrication process as for conventional DRAMs. The low-noise quasi-folded data-line architecture allows the data-line capacitance to be one eighth the conventional value at the minimum, or the number of cells per amplifier to be 64 times the conventional number at the maximum. In addition, this architecture provides a more relaxed layout for the READ/WRITE circuits. The operation of four series-connected cells is observed successfully through a test device which includes a voltage-to-current conversion circuit, a current-mirror amplifier, and a 0.76- mu m/sup 2/ crown-shaped stack-capacitor (STC) cell. >

A single 1.5-V digital chip for a 10/sup 6/ synapse neural network

A digital-chip architecture for a 10(6)-synapse neural network is proposed. It runs on a 1.5-V dry cell to allow its use in portable equipment. An on-chip DRAM cell array stores synapse weights digitally to provide easy programmability and automatic refreshing. A pitch-matched interconnection and a combinational unit circuit for summing product allow a tight layout. A dynamic data transfer circuit and the 1.5-V operation of the entire chip reduce the power dissipation, but the parallel processing nonetheless provides high speed at the 1.5-V supply. Estimated power dissipation of 75 mW and a processing speed of 1.37 giga connections per second are predicted for the chip. The memory and the processing circuits can be integrated on a 15.4-mmx18.6-mm chip by using a 0.5-mum CMOS design rule. A scaled-down version of the chip that has an 8-kb DRAM cell array was fabricated, and its operation was confirmed.

A low-impedance open-bitline array for multigigabit DRAM

The noise-generating mechanisms inherent in the open-bitline DRAM array using the 6F/sup 2/ (F: feature size) memory cells and techniques for reducing the noise are described. The sources of differential noise coupled to the paired bitlines laid out in two arrays are the p-well, cell plate, and the group of nonselected wordlines. It was found, by simulation and by experiment with a 0.13-/spl mu/m 256-Mb test chip, that the level of noise is dramatically reduced by using a low-impedance array with careful layout featuring low-resistivity materials, tight bridging between pairs of adjacent arrays, and a small array, achieving a comparable level of noise to that seen in the twisted and folded-bitline array. On basis of these results, it turns out that the open-bitline array has a strong chance of revival in the multigigabit generation, as long as these noise reduction techniques are applied.

A 0.4-/spl mu/m/sup 2/ self-aligned contactless memory cell technology suitable for 256-Mbit flash memories

This paper describes advanced self-aligned contactless memory-cell technology with sector erase and programming operations for a single power supply 256-Mbit flash memory. Using new self-aligned field-isolation technology and a deep punch-through stopper while minimizing the thermal budget of memory-cell fabrication process, 0.40-/spl mu/m/sup 2/ cells based on 0.25-/spl mu/m CMOS processes are fabricated.<<ETX>>