Hideharu Kyouda

Advanced multi-patterning using resist core spacer process for 22nm node and beyond

Self-aligned double patterning (SADP) such as multi-patterning process seems to be the most promising technology for 22nm node devices and beyond. In recent years, in order to further scaling, other multi-patterning processes such as self-aligned triple patterning (SATP) and self-aligned quadruple patterning (SAQP) have also been studied. However, process cost and CD controllability are major challenges since multi-patterning technology utilizes spacer processes which-requires a larger number of etching and deposition process steps. And then we began to study the simplified spacer process using resist core and we verified its process performance (Process window, LWR) This paper reports on the results of a comprehensive process evaluation of multi-patterning technology using lithography clusters, etching and deposition tools.

High-etching selectivity of spin-on-carbon hard mask process for 22nm node and beyond

As part of the trend toward finer semiconductor design rules, the resist film thickness is getting thinner, and the etching technology that uses resist masking is getting more difficult. To solve such a problem in recent years, the film structure used in the resist process also is changing from the single-layer process (BARC and resist stacked film) to the multi-layer process (Carbon hard-mask, middle layer and resist stacked film) The carbon hard-mask of multi-layer process can be divided into two kinds, which are the CVD-carbon (CVD-C) that uses the chemical vapor deposition method and Spin-on-carbon (SOC) that uses the spin-coating method. CVD-C is very attractive for ensuring the high etching selection ratio, but still has major challenges in particle reduction, lower planarization of substrate and high process cost. On the other hand, SOC is very attractive for low cost process, high level of planarization of substrate and no particles. Against this background, we verify the development of the SOC that had the high etch selection ratio by improving etching condition, material and SOC cure condition. Moreover, we can fabricate below 30nm SiO2 patterning and the possibility of development with extreme ultraviolet lithography (EUVL) was suggested. This paper reports on the results of a comprehensive process evaluation of a SOC based multi-layer technology using lithography clusters, etching tools.

Process performance of novel resist material and novel coater/developer system for cross-line contact hole process

Double patterning techniques are one of the dominant method to achieve the 32 nm node and beyond and Litho-Litho- Etch (LLE) process is a strong candidate for double patterning method. Contact hole resolution is limited by the low image contrast using dark field masks. Cross-line contact hole process using LLE process is applicable to image fined contact holes. Contact hole patterns are formed by first line and space patterns and orthogonal second line and space patterns. Furthermore LLE process flow should be simple as possible as it can for cost reduction. Thus LLE process without freezing process is ideal one. In this paper, we examine the process performance using latest material for freezing free LLE process, exposure tool and novel coater/developer system. The latest resist materials can form cross-line contact hole with good pattern fidelity and CD uniformity. It will be shown that novel coater/developer hardware is effective on enhancement of lithography performance like CD control and defect control toward double Patterning technology for 193-nm immersion lithography.

Immersion-cluster uptime enhancement technology toward high-volume manufacturing

In immersion lithography, importance is placed on technology for controlling coating along the edge of the wafer. In the case of a top-coat process, it has been observed that the top coat can peel off during immersion exposure due to weak adhesion to the substrate, a characteristic of top-coat films. The peeling of the film is thought to adversely affect immersion-exposure equipment and the wafer surface by the formation of defects due to the contamination of the immersion-exposure tool and by residual particles. Nikon Corporation and Tokyo Electron Ltd. (TEL) have performed joint research and development in response to these problems. TEL has studied rinsing technology for the wafer edge section and established coating processes and control techniques that rinse the edge section to remove foreign matter and that control the cutting position of each film in the edge section. TEL has developed new processes and hardware to remove foreign matter introduced into the immersion-exposure tool, and has shown that this technology can help prevent contamination of exposure equipment. Nikon has established efficient on-body periodic rinsing as a new technology for exposure equipment that can reduce defect.

193-nm immersion lithography for high volume manufacturing using novel immersion exposure tool and coater/developer system

The demand for more highly integrated semiconductor devices is driving efforts to reduce pattern dimensions in semiconductor lithography. It has been found that 193-nm immersion lithography can achieve smaller patterns without having to modify the infrastructure used for existing state-of-the-art 193-nm dry lithography. As a result, 193-nm immersion lithography is a promising technology for use in mass production processes. Recently, the scanning speed of the exposure stage has been increasing in order to achieve high throughput for mass production. Currently, the topcoat process is one of the promising candidates for this high speed scanning process. On the other hand, the non topcoat resist process is being tested from a C.O.O. (cost of ownership) point of view. However, there are some important points that become apparent, such as specific defect countermeasures and wafer bevel control. Nikon and TEL developed the novel immersion exposure tool and coater/developer system application technology in order to solve these immersion specific issues. In this paper, we examine the process performance using novel immersion exposure tool and coater/developer system.