Hideki Gomi

A degradation-free Cu/HSQ damascene technology using metal mask patterning and post-CMP cleaning by electrolytic ionized water

A Cu/HSQ damascene structure can be achieved by a new HSQ patterning technology using a TiN mask and post-CMP cleaning with electrolytic ionized ultra-pure cathode water. A Cu/HSQ structure with capacitance 17% lower than that of HSQ patterned by a conventional photo-resist-mask process was successfully fabricated with a sufficiently small number of post-Cu-CMP particles, only 30% of that with conventional post-Cu-CMP cleaning.

The Influence of Fluorine Desorption from ECR-CVD SiOF Film

The influence of fluorine desorption from SiOF films deposited by biased ECR-CVD was studied. It was found that desorbed F atoms from the SiOF film react with Ti suicide film resulting in forming SiF4 gas. The evolution of SiF4 gas caused the peel-off of the films.

Stability and Application to Multilevel Metallization of Fluorine-Doped Silicon Oxide by High-Density Plasma Chemical Vapor Deposition

We report the application of biased high-density-plasma-chemical-vapor-deposited (HDP-CVD) SiOF films to multilevel metallization technology. We discuss the reason for the SiOF films low dielectric constant and illustrate the optimal deposition conditions. The fluorine concentration in the HDP-CVD SiOF film can affect the gap filling characteristics. We observed that the dielectric constant of this SiOF film is 3.7 for a fluorine concentration of 7.3 at.%. This film was successfully applied to intermetal dielectrics and the parasitic capacitance was 13% lower than that of a SiO2 film.

A 0.7-µm-Pitch Double Level Al Interconnection Technology for 1-Gbit DRAMs using SiO2 Mask Al Etching and Plasma Enhanced Chemical Vapor Deposition SiOF

A 0.7-µm-pitch double level aluminum (Al) interconnection technology on a 1-µm-high step is established for 1-Gbit dynamic random access memories (DRAMs). A SiO2 film which has a high resistance to Al etching was used as the mask layer. 0.35-µm-width Al wirings were fabricated even on a 1-µm-high step. 0.2-µm-spaces (aspect ratio=2.5) between the taper shaped Al lines were filled, for the first time, by a plasma enhanced chemical vapor deposition (PECVD) fluorine doped silicon oxide (SiOF) film (e=3.9). The SiOF film capped with the PECVD SiO2 film has enough stability for the process integration. It was confirmed that these technologies can be applied to a double level Al interconnection using a 0.3-µm-diameter tungsten (W) plug.

Integration Issues for Low Dielectric Constant Materials in each Generation of ULSI'S

The technologies utilizing Fluorinated Silicon Oxide (FSG, k=3.6) and Hydrogen Silsesquioxane (HSQ, k=3.0) have been established for 0.25-µm and 0.1 8-µm generation ULSIs. However, low-k materials for the next generation ULSIs, which have a dielectric constant of less than 3.0, have not become mature yet. In this paper, we review process integration issues in applying FSG and HSQ, and describe integration results and device performance using Fluorinated Amorphous Carbon (a-C:F, k=2.5) as one of the promising low-k materials for the next generation ULSIs.

New via formation process for suppressing the leakage current between adjacent vias for hydrogen silicate based inorganic SOG intermetal dielectric

The leakage current between the adjacent vias in case of hydrogen silicate based inorganic spin-on glass (HSI-SOG) intermetal dielectric (IMD) is investigated for 0.6 /spl mu/m pitch multilevel interconnection with borderless vias. We propose a new via formation process using an NH/sub 3/ plasma treatment to decrease this leakage current by protecting the via sidewalls. The leakage level is considerably suppressed by this NH/sub 3/ plasma treatment. The dielectric constant of HSI-SOG is maintained at a low level. This technology is essential to high-performance sub-0.25 /spl mu/m CMOS devices with HSI-SOG IMD.

RC delay reduction of 0.18 /spl mu/m CMOS technology using low dielectric constant fluorinated amorphous carbon

A low-k fluorinated amorphous carbon (a-C:F: dielectric constant 2.5) film as inter-metal dielectric (IMD) has been successfully integrated in 0.18-/spl mu/m CMOS technology. The RC delay of a ring oscillator with loaded wiring (length: 10 mm) is reduced by 22% using an a-C:F IMD compared with that using a SiO/sub 2/ IMD. The thermal stability problems from integrating a-C:F IMD with a W plug (deposition temperature: 370/spl deg/C; film stress: 1.5/spl times/10/sup 10/ dyne/cm/sup 2/) can be overcome by using post a-C:F deposition anneal. This leads to less a-C:F outgassing at temperatures up to 375/spl deg/C.