Noriaki Oda

A high reliability copper dual-damascene interconnection with direct-contact via structure

A new via technology for improving electromigration (EM) reliability of copper (Cu) dual-damascene (DD) interconnection has been developed. Early failure mode of a conventional Cu DD structure is found as void formation at the via-bottom interface, where flux divergence of Cu ions is large due to diffusion barrier-layer. In order to avoid the early failures, direct-contact via (DCV) technology whose concept is “barrier-free” at the via-bottom has been developed. The early failure mode is eliminated by the DCV technology and lower via resistance is obtained.

A model for evaluating cumulative oxide damage from multiple plasma processes

This paper reports a model for evaluating the cumulative oxide damage caused by multiple plasma processes. By considering dependence of the charging current on the antenna size, the damage to a MOS device with various antenna configurations is evaluated, and is compared with the measured data. It is shown that the plasma charging current is a sub-linear function of the antenna size. Because of this characteristic, cumulative oxide damage becomes smaller than a simple sum when the antenna is shared among multiple layers of antenna conductors. A modified antenna rule is proposed, and a realistic antenna design guideline is obtained.

Electromigration Lifetime Enhancement of CoWP Capped Cu Interconnects by Thermal Treatment

In order to develop highly reliable Cu interconnects, temperature dependence of the electromigration (EM) lifetime of metal (CoWP) capped Cu interconnects is investigated. It is found that the EM lifetime is enhanced as the test temperature rise from 275 to 380 °C. NH3 plasma treatment before the dielectric cap layer deposition on the CoWP capped Cu interconnects influenced the temperature dependence of EM lifetime, that is, the interconnects without the NH3 plasma treatment have longer EM lifetime than those with the NH3 plasma treatment at the higher test temperatures. In order to investigate the mechanism for this lifetime enhancement, micro-analysis and failure mode analysis were carried out. It is concluded that the Co alloying with Cu and the CoWP coverage repair due to Co diffusion at the high temperature lead to the EM lifetime enhancement.

Feasibility Study of 45-nm-Node Scaled-Down Cu Interconnects With Molecular-Pore-Stacking (MPS) SiOCH Films

A feasibility study was done for 45-nm-node Cu interconnects using a novel molecular-pore-stacking (MPS) SiOCH film (k = 2.45), taking electron scattering in the scaled-down Cu lines into consideration. The as-deposited MPS SiOCH film, formed by plasma polymerization of a robust six-member-ring (hexagonal) siloxane with large steric-hindered hydrocarbon side chains, has self-organized subnanometer pores. An oxidation-damage-free dual-hard-mask etching process, along with a benzocylobuten liner technique, preserved the low permittivity of the MPS film in the Cu lines, with excellent interline dielectric reliability. The line aspect ratio was also balanced to decrease not only the interconnect parasitic capacitance but also the Cu line resistivity, which is increased by the electron scattering in the narrow lines. By combining the above etching process and the line-aspect control, the feasibility of the MPS SiOCH film was confirmed with outstanding performance and excellent reliability for the 45-nm-node ultralarge scale integrations

A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation

A robust embedded ladder-oxide (k=2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 µm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 µm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

Defect isolation and characterization in contact array/chain structures by using voltage contrast effect

Voltage contrast effect measurement, a conventional technique for isolating open contacts, was applied to high-resistance contact isolation. The detectable lower limit was clarified experimentally and theoretically. The passive voltage contrast effect is a transitional phenomenon, so the analysis conditions must be optimized for the device properties and primary beam irradiation. The detectable lower resistance limit was 1E9 /spl Omega/ at most. The biased voltage contrast effect is steady state, so it could be used to isolate failed via modules whose resistance was 1E4-1E5 /spl Omega/, even when the current of the primary beam was small.

Feasibility study of 70nm pitch Cu/porous low-k D/D integration featuring EUV lithography toward 22nm generation

A feasibility study of 70 nm pitch 2-level dual damascene interconnects featuring EUV lithography is presented. Using Ru barrier metal and scalable porous silica (Po-SiO, k=2.1), a low resistivity below 4.5 µΩcm and a 13 % reduction in wiring capacitance compared with porous SiOC (k=2.65) was obtained. The predicted circuit-performance using Po-SiO was 10 % higher than that with porous SiOC. The electromigration reliability in 22 nm generation was consistent with the previous generations. The merit of EUV lithography on circuit design was also clarified.

Time-Dependent Dielectric Breakdown Characterization of 90- and 65-nm-Node Cu/SiOC Interconnects with Via Plugs

As the wiring-space decreases, the time-dependent dielectric breakdown (TDDB) of Cu/low-dielectric constant (k) interconnects becomes a critical reliability issue and more accurate prediction of the TDDB lifetime will be required. In this investigation, TDDB dependences on temperature and electric field are studied comprehensively for 90- and 65-nm-node Cu/SiOC interconnects using practical multilevel test structures with via plugs. Low-electric-field TDDB tests down to 1 MV/cm were carried out by a package TDDB method with high temperature up to 300 °C. Linear dependence of the TDDB lifetime on the electric-field is observed down to 1 MV/cm, and this suggests that the lifetime can be predicted using the E-model. The linear dependence of the TDDB lifetime on temperature is also observed up to 300 °C at 1.8 MV/cm. The activation energies for the 90 and 65 nm nodes are almost the same values, 0.76 eV for the 90 nm node and 0.74 eV for the 65 nm node. Failure is observed at the interfaces between the cap dielectric (SiCN) and the silicon dioxide layer with a surface polished by chemical-mechanical polishing (CMP) for both nodes. It is noted that no difference in the failure modes is seen between dense SiOC for the 90 nm node and porous SiOC for the 65 nm node, in spite of the different materials used for the intermetal dielectrics. This suggests that the polished interfaces greatly affect on the TDDB lifetime for both nodes. Improved TDDB lifetime is obtained by increasing the post-CMP cleaning time and the pretreatment time before the cap dielectric deposition. Sufficient TDDB lifetimes of over 10 years under practical operating conditions are obtained for both 90- and 65-nm-node Cu/low-k interconnects with via plugs.

Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects

Molecular-pore-stacking (MPS), SiOCH films (k=2.4) are integrated in 45nm-node Cu interconnects with 140nm-pitched lines and 70nm-vias, and the feasibility is confirmed. The MPS film, which is deposited by plasma-polymerization of robust ring-type siloxane molecules, has the self-organized, porous structure with reinforcing the mechanical properties. The low permittivity is sustained in the 140nm-pitched lines by oxidation-damage-free etching, and the inter-line dielectric reliability is confirmed along with the BCB pore-seal technique, estimating 15.9% reduction in the 70nm-spaced, line capacitance refer to that of the 65nm-node SDIs. The MPS/Cu interconnect is one of the strong candidates for 45nm-node ULSI devices.

Dual Damascene Interconnect Technology for 130-nm-node Complementary Metal–Oxide–Semiconductor Devices Using Ladder-Oxide Film

A 0.34-µm-pitch Cu dual damascene interconnect technology using a low-k ladder-oxide film (k=2.9) is developed for 130-nm-node complementary metal oxide semiconductor (CMOS) devices. Photoresist poisoning was improved by adopting the ladder-oxide film with annealing before the photolithography step. The fence structures around via openings caused poor Cu gap filling. The problem was solved by controlling the filling height of a bottom anti-reflective coating and by eliminating the photoresist poisoning. Furthermore, no degradation of the ladder-oxide film upon photoresist stripping was observed. It was demonstrated that these technologies could be applied to a product-level application-specific integrated circuit chip with a seven-level Cu interconnect.