Susumu Hatano

High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic (XTL) interface

Crosstalk Transfer Logic (XTL) is a digital-signal interface that uses directional couplers to form parallel lines within a circuit board. An advantage of the XTL is that it provides a multi-drop and high-speed system that is a one-to-many connection that can be used as a memory bus. To evaluate the signal integrity of an XTL to be applied to a DRAM bus, a test chip and boards were developed. We describe the design of the bus and report the results of its evaluation in this paper. The test chip was designed using a 0.15-/spl mu/m CMOS process and it had a controllable offset of the hysteresis receiver. A folding coupler was applied to the motherboard to condense the wiring and to reduce the noise from adjacent signals. The mother-board had only two coupler layers, with a four-byte data width, and it was capable of having eight modules mounted on the bits. The experimental results showed that the WRITE and READ operation reached speeds of at least 500 Mbps when eight modules were mounted on the bus.

Design of a second-level cache chip for shared-bus multimicroprocessor systems

The design of a second-level cache chip with the most suitable architecture for shared-bus multiprocessing is described. This chip supports high-speed (160-MB/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. The chip, which supports a 50-MHz CPU and uses 0.8 mu m CMOS technology, includes a 32 kB data memory, 42 kb tag memory. and 21.7 K-gate logic. >

Low-cost, Low-noise Vref Design for High-speed DDR Memory Modules

This paper discusses new Vref designs for high-speed memory modules. Our designs include chip resistors in series with Vref traces that reduce the total noise. We confirmed reduced noise of half the original through experiments

A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board Simulatig Actual Memory Module

Aiming to achieve double data rate-synchronous DRAM (DDR-SDRAM) at low-cost and with high noise tolerance by setting adequate Vref target impedance, we have established a measurement setup for Vref noise tolerance of DDR2-SDRAM on test board simulating actual memory module and measured various properties. The measured Vref noise tolerance has strong frequency-dependency; the higher the frequency, the larger the noise tolerance. We believe that this is because the intrinsic low pass filter consisted of on-chip electrical components in the test chip.