Hideko Oodaira
Toshiba
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Publication
Featured researches published by Hideko Oodaira.
IEEE Journal of Solid-state Circuits | 1991
Masaki Momodomi; Tomoharu Tanaka; Yoshihisa Iwata; Yoshiyuki Tanaka; Hideko Oodaira; Y. Itoh; Riichiro Shirota; Kazunori Ohuchi; F. Masuoka
Described is a 5-V-only 4-Mb (512K*8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V/sub t/) distribution, controlled by a novel program-verify technique. A tight programmed V/sub t/ distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm*15.31 mm is achieved using 1.0 mu m design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance. >
IEEE Journal of Solid-state Circuits | 1990
Yoshihisa Iwata; Masaki Momodomi; Tomoharu Tanaka; Hideko Oodaira; Y. Itoh; R. Nakayama; R. Kirisawa; Seiichi Aritome; Tetsuro Kikuna Endoh; Riichiro Shirota; Kazunori Ohuchi; F. Masuoka
A high-density, 5-V-only, 4-Mb CMOS EEPROM with a NAND-structured cell using Fowler-Nordheim tunneling for programming is discussed. The block-page mode is utilized for high-speed programming and easy microprocessor interface. On-chip test circuits for shortening test time and for evaluating cell characteristics yield highly reliable EEPROMs. The NAND EEPROM has many applications for microcomputer systems that require small size and large nonvolatile storage systems with low power consumption. >
international solid-state circuits conference | 1995
Yoshihisa Iwata; Kenichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Hideko Oodaira; Masaki Momodomi; Yasuo Itoh; T. Watanabe; H. Araki; Kazuhito Narita; K. Masuda; J.-I. Miyamoto
A 32 Mb NAND type flash EEPROM in 0.425 /spl mu/m CMOS achieves 35 ns cycle time for data read-out and programming data load by adopting a pipeline scheme. Metal-strapped select gates and boosted word line reduce read-out access time. Tight-programmed cell Vth distribution can be realized by program verify, using a simplified data register circuit. Multiple blocks can be erased at the same time by adopting erase block registers for each block. Simultaneous-erase verify for one block reduces total erase time. All funtions require only 3.3 V power supply.
symposium on vlsi circuits | 1992
Tomoharu Tanaka; Yoshiyuki Tanaka; Hiroshi Nakamura; Hideko Oodaira; Seiichi Aritome; Riichiro Shirota; F. Masuoka
A quick program/program verify architecture with an intelligent verify circuit for 3-V-only NAND-EEPROMs is described. The verify circuit, which is composed of two transistors, provides a simple, intelligent program algorithm for 3-V-only operation. The total programming time is reduced to 50%. By using intelligent verify circuits, the memory cells which require more time to reach the program state are automatically detected. Verify-read, the modification of program data, and data reload are performed simultaneously. The chip size penalty is estimated to be only 1% for a 16-Mb NAND-EEPROM.<<ETX>>
symposium on vlsi circuits | 1990
Tomoharu Tanaka; M. Momodomi; Yoshihisa Iwata; Yoshiyuki Tanaka; Hideko Oodaira; Y. Itoh; Riichiro Shirota; Kazuya Ohuchi; F. Masuoka
The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin p-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design
international electron devices meeting | 1988
Masaki Momodomi; R. Kirisawa; R. Nakayama; Seiichi Aritome; Tetsuro Kikuna Endoh; Y. Itoh; Yoshihisa Iwata; Hideko Oodaira; Tomoharu Tanaka; Masahiko Chiba; Riichiro Shirota; F. Masuoka
Novel device technologies for a 5-V-only EEPROM (electrically erasable programmable read-only memory) with a NAND structure cell are described. By applying half of the programming voltage to unselected bit lines and a successive programming sequence, the NAND structure cell keeps a wide threshold margin. A high-voltage CMOS process realizes reliable programming characteristics. The reliability of the cell has been confirmed experimentally. Using 1.0- mu m design rules, the unit cell area per bit is 12.9- mu m/sup 2/, which is small enough to realize a 4-Mb EEPROM.<<ETX>>
The Japan Society of Applied Physics | 1976
Hiroshi Watanabe; Hiroshi Nakamura; Kazuhiro Shimizu; Seiichi Aritome; Toshitake Yaegashi; Yuji Takeuchi; Kenichi Imamiya; Ken Takeuchi; Hideko Oodaira
Archive | 1994
Yasuhisa Takeyama; Junichi Miyamoto; Yoshihisa Iwata; Hironori Banba; Hideko Oodaira
Archive | 2010
Hiroshi Nakamura; Ken Takeuchi; Hideko Oodaira; Kenichi Imamiya; Kazuhito Narita; Kazuhiro Shimizu; Seiichi Aritome
Archive | 2000
Yoshihisa Iwata; Hideko Oodaira