Hidenari Nakashima

ULSI interconnect length distribution model considering core utilization

Interconnect length distribution (ILD) represents a correlation between the number of interconnects and length. The ILD can predict power consumption, clock frequency, chip size, etc. It has been said that high core utilization and small circuit area improve chip performance. We propose a ILD model to predict a correlation between core utilization and chip performance. The proposed model predicts influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decrease of load capacitance is more important than that of total interconnect length for improvement of chip performance. The proposed ILD model expresses actual ILD more accurate than conventional models.

Derivation of interconnect length distribution in X architecture LSIs

The prediction model for the interconnect length distribution (ILD) in LSIs with orthogonal interconnects based on Rents empirical rule is extended to the prediction of ILD for the X Architecture containing diagonal interconnects and all-directional interconnects. The effectiveness of the X Architecture is evaluated based on the new prediction model.

Fast Methods to Estimate Clock Jitter due to Power Supply Noise*This paper was presented at Karuizawa Workshop.

In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before floor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verification stage after place-and-route of the chip. For an example design, the relative difference between clock jitter estimated at the initial design stage and that of the design verification stage is 23%. The example result also shows that the proposed method for the verification stage is about 24 times faster than the conventional one to analyze clock jitter.

Wire length distribution model considering core utilization for system on chip

This paper presents a new model to estimate wire length distribution (WLD) of system on chip (SoC). The WLD represents a correlation between wire length and the number of interconnect, and we can predict power consumption, maximum clock frequency, chip size, etc with the WLD. The proposed model provides a WLD considering each core utilization of several macro blocks in a system LSI. We present an optimization method to determine each core utilization.

Wire Length Distribution Model for System LSI

This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.

Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

Proposal of Metrics for SSTA Accuracy Evaluation*This paper was presented at Karuizawa Workshop. The work was conducted as an activity of physical design standardization study group, EDA technical committee of Japan Electronics and Information Technology Industries Association (JEITA).

With the recent advance of process technology shrinking, process parameter variation has become one of the major issues in SoC designs, especially for timing convergence. Recently, Statistical Static Timing Analysis (SSTA) has been proposed as a promising solution to consider the process parameter variation but it has not been widely used yet. For estimating the delay yield, designers have to know and understand the accuracy of SSTA. However, the accuracy has not been thoroughly studied from a practical point of view. This paper proposes two metrics to measure the pessimism/optimism of SSTA; the first corresponds to yield estimation error, and the second examines delay estimation error. We apply the metrics for a problem which has been widely discussed in SSTA community, that is, normal-distribution approximation of max operation. We also apply the proposed metrics for benchmark circuits and discuss about a potential problem originating from normal-distribution approximation. Our metrics indicate that the appropriateness of the approximation depends on not only given input distributions but also the target yield of the product, which is an important message for SSTA users.

Optimization Methodology of Layer Numbers with Circuit/Process Co-Design

The number of layers directly affects manufacturing cost, and it also has a trade-off with the circuit area in multilevel interconnection LSI. In this paper, we propose a co-design methodology for circuits and processes to optimize the number of interconnect layers. In the proposed methodology, the number of interconnect layers can be optimized in consideration of circuit area. Wire length distribution (WLD) is used to derive the optimized number of layers from a circuit netlist. Operating frequency and power consumption are estimated as functions of circuit area in the 180 nm process-technology node. From the analyzed results, it has been shown that circuit area has an optimum value to improve both operating frequency and power consumption.

Evaluation of X Architecture Using Interconnect Length Distribution

In this paper, we propose a new Interconnect Length Distribution (ILD) model to evaluate X architecture. X architecture uses 45°-wire orientations in addition to 90°-wire orientations, which contributes to reduce the total wire length and the number of vias. In this paper, we evaluated interconnect length distribution of diagonal (45° orientations) and all-directional wiring. The average length and the longest length of interconnect are estimated, and 18% reduction in power consumption and 17% improvement in clock frequency can be obtained by the diagonal wiring in the experimental results. The all-directional wiring does not have large advantage as compared the diagonal wiring.

Optimization methodology of global interconnect structure

The optimal interconnect structure is required because circuit performance depends on resistance and capacitance in interconnects. This paper proposes the optimization methodology of interconnect structure based on the wire length distribution (WLD) model. Using the proposed method, metal height and ILD thickness of global interconnect layer in 65 nm node become larger than the ITRS structure. Compared with the ITRS structure, the delay time can be improved by 9% and 22% for complex and simple circuits, respectively.