Takaaki Okumura

Gate delay estimation in STA under dynamic power supply noise

This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 2% error on average.

Setup time, hold time and clock-to-Q delay computation under dynamic supply noise

This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold time on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.

A minimum decap allocation technique based on simultaneous switching for nanoscale SoC

In this paper, we propose a novel decoupling capacitance (decap) optimization technique based on simultaneous cell switching activity at the pre-layout stage. White space in the form of cell padding for the required quantity of decap is added to cells which simultaneously switch during the peak noise period, which is quickly estimated using initial timing information and the current waveforms for each cell instance, without the need to reference the power grid. The method is applied to an actual 45nm LSI and results show a 35% decap area reduction or 21.9% peak noise reduction compared with conventional decap insertion flows. The technique can improve the reliability of SoC with a runtime overhead of only 1% at the P&R stage in existing nanoscale SoC EDA design flows.

A Method to Derive SSO Design Rule Considering Jitter Constraint*This paper was presented at Karuizawa Workshop. The work was conducted as an activity of physical design methodology study group, EDA technical committee of Japan Electronics and Information Technology Industries Association (JEITA).

A method to derive design rules for SSO (Simultaneous Switching Outputs) considering jitter constraint on LSI outputs is proposed. Since conventional design rules do not consider delay change caused by SSO, timing errors have sometimes occurred in output signals especially for a high-speed memory interface which allows very small jitter. A design rule derived by the proposed method includes delay change characteristics of output buffers to consider the jitter constraint. The rule also gives mapping from the jitter constraint to constraint on design parameters such as effective power/ground inductance, number of SSO and drivability of buffers.

Proposal of Metrics for SSTA Accuracy Evaluation*This paper was presented at Karuizawa Workshop. The work was conducted as an activity of physical design standardization study group, EDA technical committee of Japan Electronics and Information Technology Industries Association (JEITA).

With the recent advance of process technology shrinking, process parameter variation has become one of the major issues in SoC designs, especially for timing convergence. Recently, Statistical Static Timing Analysis (SSTA) has been proposed as a promising solution to consider the process parameter variation but it has not been widely used yet. For estimating the delay yield, designers have to know and understand the accuracy of SSTA. However, the accuracy has not been thoroughly studied from a practical point of view. This paper proposes two metrics to measure the pessimism/optimism of SSTA; the first corresponds to yield estimation error, and the second examines delay estimation error. We apply the metrics for a problem which has been widely discussed in SSTA community, that is, normal-distribution approximation of max operation. We also apply the proposed metrics for benchmark circuits and discuss about a potential problem originating from normal-distribution approximation. Our metrics indicate that the appropriateness of the approximation depends on not only given input distributions but also the target yield of the product, which is an important message for SSTA users.